40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

2.7.1. Testbenches with Adapters

Figure 5. 40-100GbE IP Core Testbenches with Adapters Illustrates the top-level modules of the non-40GBASE-KR4 40GbE and 100GbE example testbenches that use adapters. In the file names, * denotes 40 for 40GbE IP cores and 100 for 100GbE IP cores.
Figure 6. 40GBASE-KR4 40GbE IP Core Testbench with Adapters Illustrates the top-level modules of the 40GBASE-KR4 example testbench that uses adapters. To support the simulation of auto-negotiation, the testbench uses two instances of the IP core instead of configuring the IP core in loopback mode.
Table 16.  40-100GbE IP Core Testbench with Adapters File DescriptionsLists the key files that implement the example testbenches.

File Names

Description

Testbench and Simulation Files

alt_40gbe_tb.sv, alt_e40_avalon_kr4_tb.sv, alt_100gbe_tb.v

The testbench wrapper file. For non-KR4 variations, this file includes all of the testbench modules.

alt_e40_avalon_tb_packet_gen.v

The packet generator. This file is present only for 40GBASE-KR4 variations.

alt_e40_avalon_tb_packet_gen_sanity_check.v

The packet checker. This file is present only for 40GBASE-KR4 variations.

alt_e40_avalon_tb_sample_tx_rom.hex

The sample TX ROM. This file is present only for 40GBASE-KR4 variations.

alt_e40_avalon_tb_sample_tx_rom.v

Lists the contents of the sample TX ROM (alt_e40_avalon_tb_sample_tx_rom.hex). This file is present only for 40GBASE-KR4 variations.

Testbench Scripts

run_vsim.do

The ModelSim script to run the testbench.

run_vcs.sh

The Synopsys VCS script to run the testbench.

run_ncsim.sh

The Cadence NCSim script to run the testbench.

Figure 7. Typical 40GbE Traffic on the Avalon-ST Interface Using the Four- to Two-Word AdaptersShows typical traffic from the simulation testbench created using the < instance_name >_example/alt_e40_e100/example_testbench/run_vsim.do script in ModelSim.
Note: Client logic must maintain the l4_tx_valid signal asserted while asserting SOP, through the assertion of EOP. Client logic should not pull this signal low during a packet transmission.

The markers in the figure show the following sequence of events:

  1. At marker 1, the application asserts l4_tx_startofpacket, indicating the beginning of a TX packet.
  2. At marker 2, the application asserts l4_tx_endofpacket, indicating the end of the TX packet. The value on l4_tx_empty[4:0] indicates that the 2 least significant bytes of the last data cycle are empty.
  3. At marker 3, the IP core asserts l4_rx_startofpacket, indicating the beginning of an RX packet. A second transfer has already started on the TX bus.
  4. At marker 4, the 40GbE IP core deasserts l4_rx_valid, indicating that the IP core does not have new valid data to send to the client on l4_rx_data[255:0]. l4_rx_data[255:0] remains valid and unchanged for a second cycle.
  5. A marker 5, the 40GbE IP core asserts l4_rx_valid, indicating that the it has valid data to send to the client on l4_rx_data[255:0].
  6. At marker 6, the 40GbE IP core deasserts l4_rx_valid, indicating that it does not have new valid data to send to the client on l4_rx_data[255:0]. l4_rx_data[255:0] remains unchanged for a second cycle.
  7. At marker 7, the 40GbE IP core asserts l4_rx_valid, indicating that the it has valid data to send to the client on l4_rx_data[255:0].
  8. At marker 8, the 40GbE IP core deasserts l4_rx_valid, indicating that the 40GbE IP core does not have new valid data to send to the client on l4_rx_data[255:0]. l4_rx_data[255:0] remains unchanged for a second cycle.
  9. At marker 9, the IP core asserts l4_rx_endofpacket, indicating the end of the RX packet. l4_rx_empty[4:0] has a value of 0x1D, indicating that 29 least significant bytes of the last cycle of the RX packet empty.
Note: The ready latency on the TX client interface with adapters is 0.