40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

3.4.1.1. Transceiver PHY Control and Status Registers

The TX serial rate (PCS clock) is based on the input transceiver reference clock and should be precise and stable. The RX serial rate is recovered from the remote system. The RX serial clock typically shows some instability during lock acquisition.

In variations that target a Stratix IV device, the registers in the transceiver PHY provide dynamic access to the analog configuration capability on a per channel (pin) basis. You can also use these registers to place the transceivers in loopback mode for diagnostic or error injection testing. In loopback mode, the TX output connects to the corresponding RX channel.

Table 43.  Scratch and Clock Registers for Applicable Devices

Address

Name

Applicable Device(s)

Bit

Description

HW Reset Value

Access

0x000

PHY_VERSION

Arria V GZ, Stratix IV, and Stratix V

[31:0]

40GbE/100GbE PHY IP core revision.

0x00E01310 (40GbE)

0x 00DE1310 (100GbE)

R

0x001

SCRATCH_PHY

Arria V GZ, Stratix IV, and Stratix V

[31:0]

Scratch register available for testing.

0x00000000

RW

0x002 12

CLK_TXS

Arria V GZ, Stratix IV, and Stratix V

[19:0]

TX serial clock rate monitor in KHz.

0x00000

R

0x003 12

CLK_RXS

Arria V GZ, Stratix IV, and Stratix V

[19:0]

RX serial clock rate monitor in KHz.

0x00000

R

0x004

CLK_TXC

Arria V GZ, Stratix IV, and Stratix V

[19:0]

TX core clock rate monitor in KHz.

0x00000

R

0x005

CLK_RXC

Arria V GZ, Stratix IV, and Stratix V

[19:0]

RX core clock rate monitor in KHz.

0x00000

R

0x006

Arria V GZ, Stratix IV, and Stratix V

Reserved.

0x007

Arria V GZ and Stratix V

Reserved.

0x007

GX_CTRL1

Stratix IV

[31]

When set, places the transceiver in Internal serial loopback, from TX to RX.

1’b0

RW

[30]

When asserted, the transceiver channel’s analog settings are read on the rising edge of clk_status.

1’b0

RW

[29]

When asserted, the transceiver channel’s analog settings are written on rising edge of clk_status.

1’b0

RW

[28:4]

Specifies the analog settings to write. Refer to the following table for the register fields which are read on GX_ REPLY[ 24:0]. Bits[28:4] of this register correspond to bits[24:0] of the GX_REPLY register.

0x000000

RW

[3:0]

Specifies the logical channel to select [0–9].

0x0

RW

0x008

GX_CTRL2

Arria V GZ, Stratix IV, and Stratix V

[1]

Specifies bit error inject position 1 on rising edge.

1’b0

RW

[0]

Specifies bit error inject position 0 on rising edge.

1’b0

RW

0x009

Arria V GZ and Stratix V

Reserved.

0x009

GX_REPLY

Stratix IV

[26]

Reserved.

0

R

[25]

When asserted, indicates that read data is valid.

1’b0

R

[24:0]

Contains the analog settings reported in the previous read of GX_CTRL1[28:4].

0x020080

R

Table 44.  Stratix IV Transceiver Analog Settings Register GX_CTRL1—Offset 0x007—Bits [28:4]Describes the fields in bits [28:4] of the analog settings register, GX_CTRL1. The default settings are a good starting point if you are connecting to a PMD module running at 10.3125 Gbps.

Bits

Description

HW Reset Value

Access

[28:25]

RX equalization control. The equalizer uses a pass band filter. Specifying a low value passes low frequencies. Specifying a high value passes high frequencies.

4’b0011

RW

[24:22]

RX DC gain. Sets the equalization DC gain using one of the following settings:

  • 0: 0 dB
  • 1: 3 dB
  • 2: 6 dB
  • 3: 9 dB
  • 4: 12 dB
  • 5: 15 dB
  • 6: 18 dB
  • 7: 21 dB

3’b000

RW

[21:17]

Sets the pre-emphasis for TX tap 0.

5’b10000

RW

[16:12]

Sets the pre-emphasis for TX pre-emphasis tap 1.

5’b00000

RW

[11:7]

Sets the pre-emphasis for TX pre-emphasis tap 2.

5’b10000

RW

[6:4]

TX VOD (amplitude).

3’b010

RW

If you encounter signal integrity problems using the default settings in the table, the following procedure might be helpful:

  1. Adjust VOD. A value that is too high tends to cause interference with other lanes. You should select the lowest value that functions correctly.
  2. Raise pre-emphasis tap 1 slightly. Raising tap 1 tends to help in the case of long trace length or multiple connectors causing signal loss.
  3. Adjust the equalization control. This control is roughly analogous to a stereo equalizer. It emphasizes and de-emphasizes portions of the signal by frequency.
  4. Repeat these steps, starting at step 1, making minor adjustments to all of the controls while monitoring the error rate. Note that the controls do interact.
12 When the line rate is 10.3125 Gbps, the frequency of the serial clocks clk_tx_serial and clk_rx_serial is 10312.5/40 = 257.8125 MHz.