40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

3.2.4.2. 40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface)

The adapter for the RX interface of the 100GbE IP core increases the bus width from 5 words (320 bits) to 8 words (512 bits). The adapter for the RX interface of the 40GbE IP core increases the bus width from 2 word (128 bits) to 4 words (256 bits). The Avalon-ST interface always locates the SOP at the MSB, simplifying the interpretation of incoming data.

The RX MAC acts as a source and the client acts as a sink in the receive direction.

Figure 30. RX MAC to Client Interface with Adapters The Avalon-ST interface bus width varies with the IP core variation. In the figure, <n> = 4 for the 40GbE IP core and <n> = 8 for the 100GbE IP core. <l> is log2(8*<n>).
Table 22.  Signals of the RX Client Interface with Adapters In the table, <n> = 4 for the 40GbE IP core and <n> = 8 for the 100GbE IP core. <l> is log2(8*<n>). The signals are clocked by clk_rxmac.

Name

Direction

Description

l<n>_rx_data[<n>*64-1:0]

Output

RX data.

l<n>_rx_empty[<l>-1:0]

Output

Indicates the number of empty bytes on l<n>_rx_data when l<n>_rx_endofpacket is asserted, starting from the least significant byte (LSB).

l<n>_rx_startofpacket

Output

When asserted, indicates the start of a packet. The packet starts on the MSB.

l<n>_rx_endofpacket

Output

When asserted, indicates the end of packet.

l<n>_rx_error Output When asserted, indicates an error condition.
l<n>_rx_valid

Output

When asserted, indicates that RX data is valid. Only valid between the l<n>_rx_startofpacket and l<n>_rx_endofpacket signals.

l<n>_rx_fcs_valid

Output

When asserted, indicates that FCS is valid.

l<n>_rx_fcs_error

Output

When asserted, indicates an FCS error condition.

Runt frames always force an FCS error condition. However, if a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it as a runt.

Figure 31. Traffic on the TX and RX Client Interface for 40GbE IP Core Using the Four- to Two-Word AdaptersShows typical traffic for the TX and RX Avalon-ST interface 40GbE IP core. This example shows a part of a ModelSim simulation of the parallel testbench provided with the IP core.

Figure 32. Traffic on the TX and RX Client Interface for 100GbE IP Core Using the Eight- to Five-Word AdaptersShows typical traffic for the TX and RX Avalon-ST interface of the 100GbE IP core. This example shows a part of a ModelSim simulation of the parallel testbench provided with the IP core.