40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

3.2.18.2. 40GBASE-KR4 Microprocessor Interface

The optional embedded processor interface signals allow you to use the embedded processor mode of Link Training. This mode overrides the TX adaptation algorithm and allows an embedded processor to initialize the link.

Table 31.  40GBASE-KR4 Microprocessor Interface SignalsSignals with a width of 4 x n are divided into fields of width n. Bits [n-1:0] refer to Lane 0, bits [2n-1:n] refer to Lane 1, bits [3n-1:2n] refer to Lane 2, and bits [4n-1:3n] refer to Lane 3. These signals are only available if you turn on Enable microprocessor interface.

Signal Name

Direction

Description

upi_mode_en[3:0]

Input

When a bit is asserted, enables embedded processor mode on the corresponding lane.

upi_adj[7:0]

Input

Selects the active tap for the corresponding lane. Each lane's field has the following valid values:

  • 2'b01: main tap
  • 2'b10: post-tap
  • 2'b11: pre-tap
upi_inc[3:0]

Input

When a bit is asserted, sends the increment command for the corresponding lane.

upi_dec[3:0]

Input

When a bit is asserted, sends the decrement command for the corresponding lane.

upi_pre[3:0]

Input

When a bit is asserted, sends the preset command for the corresponding lane.

upi_init[3:0]

Input

When a bit is asserted, sends the initialize command for the corresponding lane.

upi_st_bert[3:0]

Input

When a bit is asserted, starts the BER timer for the corresponding lane.

upi_train_err[3:0]

Input

When a bit is asserted, indicates a training error on the corresponding lane.

upi_lock_err[3:0]

Input

When a bit is asserted, indicates a training frame lock error on the corresponding lane.

upi_rx_trained[3:0]

Input

When a bit is asserted, the RX interface for the corresponding lane is trained.

upo_enable[3:0]

Output

When a bit is asserted, indicates that the IP core is ready to receive commands from the embedded processor for the corresponding lane.

upo_frame_lock[3:0]

Output

When a bit is asserted, indicates the receiver has achieved training frame lock on the corresponding lane.

upo_cm_done[3:0]

Output

When a bit is asserted, indicates the master state machine handshake for the corresponding lane is complete.

upo_bert_done[3:0]

Output

When a bit is asserted, indicates the BER timing for the corresponding lane is at its maximum count.

upo_ber_cnt[4*<bcw>-1:0] (width varies with <bcw> = BER counter width)

Output

Each four-bit field holds the current BER count for the corresponding lane.

upo_ber_max[3:0]

Output

When a bit is asserted, the BER counter for the corresponding lane has rolled over.

upo_coef_max[3:0]

Output

When a bit is asserted, indicates that the remote coefficients for the corresponding lane are at their maximum or minimum values.