40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

3.4.1.7. Test Pattern Counter Register

Table 50.  Test Pattern Counter Register—Offset 0x1A Unlike other statistics counters, the RX TEST_PATTERN_COUNTER is 32 bits and saturates.

Address

Name

Bit

Description

HW Reset Value

Access

0x1a

TEST_PATTERN_COUNTER

[31:0]

This register is the test pattern error counter. The counter saturates at 0xffffffff.

32’b0

R