40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Document Table of Contents
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1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core

The Altera 40- and 100-Gbps Ethernet (40GbE and 100GbE) media access controller (MAC) and PHY MegaCore® functions implement the IEEE 802.3ba 40G and 100G Ethernet Standard with an option to support the IEEE 802.3ap-2007 Backplane Ethernet Standard. This product is included in the Altera MegaCore® IP Library and available from the Quartus II IP Catalog.

This product provides support for Stratix IV, Arria V GZ, and Stratix V devices. For Arria 10 40- and 100-Gbps Ethernet support, please refer to the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide.

Note: The full product name, 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function, is shortened to 40-100GbE IP core in this document. In addition, although multiple variations are available from the parameter editor, this document refers to this product as a single IP core, because all variations are configurable from the same parameter editor.
Figure 1. 40GbE and 100GbE MAC and PHY MegaCore FunctionMain block, internal connections, and external block requirements.

As illustrated, on the MAC client side you can choose a wide, standard Avalon® Streaming (Avalon-ST) interface, or a narrower, custom streaming interface. Depending on the variant you choose, the MAC client side Avalon Streaming (Avalon-ST) interface is either 256 or 512 bits of data mapped to either four or ten 10.3125 Gbps transceiver PHY links, depending on data rate, or to four 25.78125 Gbps transceiver PHY links.

The 40GbE (XLAUI) interface has 4x10.3125 Gbps links. The 100GbE (CAUI) interface has 10x10.3125 Gbps links. Several additional options are available. For Arria V GZ, Stratix IV, and Stratix V devices, you can configure a lower-rate 40GbE option with 4x6.25 Gbps links. For Stratix V devices only, you can configure a 40GbE 40GBASE-KR4 variation to support Backplane Ethernet. For Stratix V GT devices only, you can configure a 100GbE CAUI-4 option, with 4x25.78125 Gbps links.

The FPGA serial transceivers are compliant with the IEEE 802.3ba standard XLAUI, CAUI, and CAUI-4 specifications. The IP core configures the transceivers to implement the relevant specification for your IP core variation. You can connect the transceiver interfaces directly to an external physical medium dependent (PMD) optical module or to another device.

You can configure and generate most configurations of the 40‑100GbE IP core in transmit (TX) only, receive (RX) only, or duplex mode. The 100GbE CAUI-4 option and the 40GBASE-KR4 options are available in duplex mode only.

The IP core provides standard MAC and physical coding sublayer (PCS) functions with a variety of configuration and status registers. You can exclude the statistics registers. If you exclude these registers, you can monitor the statistics counter increment vectors that the IP core provides at the client side interface and maintain your own counters.