40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683114
Date 6/15/2022
Public
Document Table of Contents

3.2.18.1. 40GBASE-KR4 Reconfiguration Interface

The 40GBASE-KR4 reconfiguration interface supports low-level control of analog transceiver properties for link training and auto-negotiation in the absence of a predetermined environment for the IP core.

Table 30.  40GBASE-KR4 Reconfiguration Interface Signals

Signals with a width of 4 x n are divided into fields of width n. Bits [n-1:0] refer to Lane 0, bits [2n-1:n] refer to Lane 1, bits [3n-1:2n] refer to Lane 2, and bits [4n-1:3n] refer to Lane 3. You can use these signals to dynamically change between auto-negotiation, link training, and normal data modes.

Note that the regular Stratix V dynamic reconfiguration interface, the reconfig_from_xcvr, reconfig_to_xcvr, and reconfig_busy signals, are also available in 40GBASE-KR4 IP core variations. The reconfiguration bundle in the example design includes the Altera Transceiver Reconfiguration Controller. For an example of how to coordinate dynamic transceiver reconfiguration using these two interfaces, the regular Stratix V transceiver reconfiguration interface and the 40GBASE-KR4 specific interface, refer to the example design reconfiguration bundle.

Signal Name

Direction

Description

rc_busy[3:0]

Input

When asserted, indicates that reconfiguration is in progress.

lt_start_rc[3:0]

Output

When asserted, starts the TX PMA equalization reconfiguration on the corresponding lane. This signal is present only if link training is enabled.

main_rc[23:0]

Output

The main TX equalization tap value, which is the same as VOD. This signal is present only if link training is enabled.

post_rc[19:0]

Output

The post-cursor TX equalization tap value for the corresponding lane. This signal is present only if link training is enabled.

pre_rc[15:0]

Output

The pre-cursor TX equalization tap value for the corresponding lane. This signal is present only if link training is enabled.

tap_to_upd[11:0]

Output

Specifies the TX equalization tap to update to optimize signal quality. Each lane's field has the following valid values:

  • 3'b100: main tap
  • 3'b010: post-tap
  • 3'b001: pre-tap

This signal is present only if link training is enabled.

seq_start_rc[3:0]

Output

When a bit is asserted, starts PCS reconfiguration for the corresponding lane.

dfe_start_rc[3:0]

Output

When a bit is asserted, starts RX DFE equalization for the corresponding lane. This signal is present only if RX equalization is enabled.

dfe_mode[7:0]

Output

Specifies the DFE operation mode. Valid at the rising edge of the def_start_rc signal and held until the falling edge of the rc_busy signal. The following encodings are defined for each lane:

  • 2'b00: Disable DFE
  • 2'b01: DFE triggered mode (single shot)
  • 2b10 and 2'b11 are reserved.

This signal is present only if RX equalization is enabled.

ctle_start_rc[3:0]

Output

When a bit is asserted, starts continuous time-linear equalization (CTLE) reconfiguration on the corresponding lane. This signal is present only if RX equalization is enabled.

ctle_rc[15:0]

Output

RX CTLE value. This signal is valid at the rising edge of the ctle_start_rc signal and held until the falling edge of the rc_busy signal. The valid range of values is 4'b0000–4'b1111. 4'b0000 indicates the RX CTLE is disabled and 4'b1111 indicates RX CTLE is at its maximum value. This signal is present only if RX equalization is enabled.

ctle_mode[7:0]

Output

Specifies the CTLE mode. This signal is valid at the rising edge of the ctle_start_rc signal and held until the falling edge of the rc_busy signal. The only valid value of this signal in the 40-100GbE IP core is 2'b0. This signal is present only if RX equalization is enabled.

pcs_mode_rc[5:0]

Output

Specifies the PCS mode for reconfiguration. Has the following valid values:

  • b'000001: auto-negotiation mode
  • b'000010: link training mode
  • b'100000: data mode (normal operation)

Other values are not valid for the 40GBASE-KR4 IP core.

en_lcl_rxeq[3:0]

Output

When a bit is asserted, it signals that an additional custom RX equalization is enabled for the corresponding lane. The bits are identical to the Link Trained status bits 0xD2 [0], [8], [16], and [24].

rxeq_done[3:0]

Input

When asserted, indicates that custom RX equalization is complete. The PHY IP core ANDs each bit of this signal with rx_trained from the Training State Diagram for the corresponding lane.

reco_mif_done

Input

Reset signal the user logic asserts after completing MIF programming.