40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
ID
683114
Date
6/15/2022
Public
Product Discontinuance Notification
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the 40GbE and 100GbE Link
A. 40-100GbE IP Core Example Design
B. Address Map Changes for the 40-100GbE IP Core v12.0 Release
C. 10GBASE-KR Registers
D. Additional Information
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Specifying the 40-100GbE IP Core Parameters and Options
2.3. IP Core Parameters
2.4. Files Generated for the 40-100GbE IP Core
2.5. Simulating the IP Core
2.6. Integrating Your IP Core in Your Design
2.7. 40-100GbE IP Core Testbenches
2.8. Simulating the 40‑100GbE IP Core With the Testbenches
2.9. Compiling the Full Design and Programming the FPGA
2.10. Initializing the IP Core
3.2.1. IP Core TX Datapath
3.2.2. IP Core TX Data Bus Interfaces
3.2.3. 40-100GbE IP Core RX Datapath
3.2.4. IP Core RX Data Bus Interfaces
3.2.5. 40GbE Lower Rate 24.24 Gbps MAC and PHY
3.2.6. 100GbE CAUI–4 PHY
3.2.7. External Reconfiguration Controller
3.2.8. Congestion and Flow Control Using Pause Frames
3.2.9. Pause Control and Generation Interface
3.2.10. Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding
3.2.11. 40-100GbE IP Core Modes of Operation
3.2.12. Link Fault Signaling Interface
3.2.13. Statistics Counters Interface
3.2.14. MAC – PHY XLGMII or CGMII Interface
3.2.15. Lane to Lane Deskew Interface
3.2.16. PCS Test Pattern Generation and Test Pattern Check
3.2.17. Transceiver PHY Serial Data Interface
3.2.18. 40GBASE-KR4 IP Core Variations
3.2.19. Control and Status Interface
3.2.20. Clocks
3.2.21. Resets
3.2.2.1. 40-100GbE IP Core User Interface Data Bus
3.2.2.2. 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
3.2.2.3. 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
3.2.2.4. Bus Quantization Effects With Adapters
3.2.2.5. User Interface to Ethernet Transmission
3.2.3.1. 40-100GbE IP Core RX Filtering
3.2.3.2. 40-100GbE IP Core Preamble Processing
3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal
3.2.3.4. 40-100GbE IP Core CRC Checking
3.2.3.5. RX CRC Forwarding
3.2.3.6. RX Automatic Pad Removal Control
3.2.3.7. Address Checking
3.2.3.8. Inter-Packet Gap
3.2.3.9. Pause Ignore
3.2.4.1. 40-100GbE IP Core User Interface Data Bus
3.2.4.2. 40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface)
3.2.4.3. 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.4.4. 100GbE IP Core RX Client Interface Examples
3.2.4.5. Error Conditions on the RX Datapath
3.4.1.1. Transceiver PHY Control and Status Registers
3.4.1.2. Lock Status Registers
3.4.1.3. Bit Error Flag Registers
3.4.1.4. PCS Hardware Error Register
3.4.1.5. BER Monitor Register
3.4.1.6. Test Mode Register
3.4.1.7. Test Pattern Counter Register
3.4.1.8. Link Fault Signaling Registers
3.4.1.9. MAC and PHY Reset Registers
3.4.1.10. PCS‑VLANE Registers
3.4.1.11. PRBS Registers
3.4.1.12. 40GBASE-KR4 Registers
3.4.1.13. MAC Configuration and Filter Registers
3.4.1.14. Pause Registers
3.4.1.15. MAC Hardware Error Register
3.4.1.16. CRC Configuration Register
3.4.1.17. MAC Feature Configuration Registers
3.4.1.18. MAC Address Registers
3.4.1.19. Statistics Registers
3.2.15. Lane to Lane Deskew Interface
The lane to lane deskew signal is included in the 40‑100GbE IP core with and without adapters. When both MAC and PHY options are selected, the lane to lane deskew input signal acts as an internal signal. The lane to lane deskew output signal from the PHY component is available to provide status information to user logic in both PHY-only and MAC and PHY IP core variations.
Signal Name |
Direction |
Description |
---|---|---|
lanes_deskewed | Input |
Indicates lane to lane skew is corrected. Available as an input to the 40-100GbE MAC IP core only. |
lanes_deskewed | Output |
Indicates lane to lane skew is corrected. Available as an output from the 40-100GbE PHY IP core and the 40-100GbE MAC and PHY IP core. |