| 2024.06.12 |
Updated the connection guidelines for the HPS_COLD_nRESET pin. |
| 2024.05.09 |
- Updated Figure: Example Power Supply Sharing Guidelines for Agilex™ 7 Devices with F-Tile and R-Tile Transceivers:
- Corrected Power Group 1 pin VCCH_SDM to VCCL_SDM.
- Fixed typo in the Power Group 2 pin VCCFUSEWR_GXF.
- Corrected the regulator sharing for VCCERT_FGT_GXF, VCCERT1_FHT_GXF, VCCERT2_FHT_GXF, and VCCRT_GXR from "Isolate" to "Share".
|
| 2024.04.01 |
- Added a note to the connection guidelines of the OSC_CLK_1 pin in Table: Dedicated Configuration/JTAG Pins to clarify about the OSC_CLK_1 QSF assignment requirement.
- Updated the connection guidelines for the VCCLSENSE and GNDSENSE pins in Table: Power Supply Pins.
- Added a note to the connection guidelines for VCCH_FGT_GXF[L,R] and VCCERT_FGT_GXF[L,R] in Table: F-Tile Power Supply Pins to clarify that you must power up all F-Tile supplies even when you are only using FHT channels.
- Added a note to the connection guidelines for REFCLK_GXR[R,L] [14A,14C,15C]_CH2P and REFCLK_GXR[R,L] [14A,14C,15C]_CH2N in Table: Agilex™ 7 R-Tile Transceiver Pins.
- Updated the following figures:
- Example Power Supply Sharing Guidelines for Agilex™ 7 Devices with P-Tile and E-Tile Transceivers
- Example Power Supply Sharing Guidelines for Agilex™ 7 Devices with F-Tile and R-Tile Transceivers
- Updated the following topic titles for clarity:
- Notes to Agilex™ 7 Device Family Pin Connection Guidelines
- Pins Status for Agilex™ 7 Devices
|
| 2023.09.26 |
- Updated the connection guidelines of the VCCFUSEWR_SDM.
- Updated the following pin names:
- APROBE_GXF_FGT[12A,12B,12C,13A,13B,13C]_Q[0,2,3]_CH3
- APROBE2_GXF_FGT[12A,12B,12C,13A,13B,13C]_Q3_CH3
- APROBE1_GXF_FHT[12A,12B,12C,13A,13B,13C]
- APROBE2_GXF_FHT[12A,12B,12C,13A,13B,13C]
- Updated the connection guidelines of the following pins:
- FHT[L,R]_RX_CH[0,1,2,3]P
- FHT[L,R]_RX_CH[0,1,2,3]N
- FGT[L,R]_RX_Q[0,1,2,3]_CH[0,1,2,3]P
- FGT[L,R]_RX_Q[0,1,2,3]_CH[0,1,2,3]N
|
| 2023.06.26 |
- Updated the connection guidelines of the VCCH_SDM pin.
- Updated the connection guidelines of the I_PIN_PERST[0,1]_N_GXR pin.
- Updated the REFCLK_GXR[R,L] [14A,14C,15C]_CH2P and REFCLK_GXR[R,L] [14A,14C,15C]_CH2N pin names in Table: Agilex™ 7 R-Tile Transceiver Pins.
- Updated the connection guidelines of the VCCERT_FGT_GXF[L,R], VCCERT1_FHT_GXF[L,R], VCCERT2_FHT_GXF[L,R], and VCCRT_GXR[L,R] pins.
- Updated the connection guidelines of the VCCFUSEWR_SDM pin in Table: Power Supply Pins.
- Updated the connection guidelines of the VCCFUSEWR_SDM pin in Table: Power Supply Sharing Guidelines for Agilex™ 7 Devices with P-Tile and E-Tile Transceivers and Table: Power Supply Sharing Guidelines for Agilex™ 7 Devices with F-Tile and R-Tile Transceivers.
- Updated the power regulator grouping in Table: Power Supply Sharing Guidelines for Agilex™ 7 Devices with F-Tile and R-Tile Transceivers.
- Updated Figure: Example Power Supply Sharing Guidelines for Agilex™ 7 Devices with F-Tile and R-Tile Transceivers.
- Retitled the document from Agilex™ 7 Device Family Pin Connection Guidelines to Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series.
|
| 2023.04.03 |
- Added a footnote for the VCCH_SDM pin in Table: Power Supply Sharing Guidelines for Agilex™ 7 Devices with F-Tile and R-Tile Transceivers.
- Updated the HPS_COLD_nRESET signal description in Table: SDM Optional Signal Pins.
- Updated the connection guidelines of the VCCH pin.
- Updated the connection guidelines of the FGT[L,R]_RX_Q[0,1,2,3]_CH[0,1,2,3]P and FGT[L,R]_RX_Q[0,1,2,3]_CH[0,1,2,3]N pins.
- Updated the connection guidelines of the VCCERT1_FHT_GXF[L,R] and VCCERT2_FHT_GXF[L,R] pins.
- Updated Table: Power Supply Sharing Guidelines for Agilex™ 7 Devices with P-Tile and E-Tile Transceivers and Table: Power Supply Sharing Guidelines for Agilex™ 7 Devices with F-Tile and R-Tile Transceivers to combine the VCCFUSEWR_SDM with VCCIO_SDM and VCCIO_HPS rails.
- Updated Table: Power Supply Sharing Guidelines for Agilex™ 7 Devices with F-Tile and R-Tile Transceivers to combine the VCCERT_FGT_GXF with VCCERT1_FHT_GXF and VCCERT2_FHT_GXF rails.
- Updated Figure: Example Power Supply Sharing Guidelines for Agilex™ 7 Devices with P-Tile and E-Tile Transceivers and Figure: Example Power Supply Sharing Guidelines for Agilex™ 7 Devices with F-Tile and R-Tile Transceivers to combine the VCCFUSEWR_SDM with VCCIO_SDM and VCCIO_HPS rails.
- Updated Figure: Example Power Supply Sharing Guidelines for Agilex™ 7 Devices with F-Tile and R-Tile Transceivers to combine the VCCERT_FGT_GXF with VCCERT1_FHT_GXF and VCCERT2_FHT_GXF rails.
|
| 2023.02.28 |
- Updated the pin description of the VCCRCORE pin.
- Updated the connection guidelines of the VCCHFUSE_GXR[L,R] pins.
|
| 2023.02.20 |
- Updated the R-Tile Transceiver Pins section to include guidelines for the Intel® Agilex™ 7 AGI041 device.
- Updated the VCCFUSEWR_SDM notes in the following tables:
- Table: Power Supply Sharing Guidelines for Intel® Agilex™ 7 Devices with P-Tile and E-Tile Transceivers
- Table: Power Supply Sharing Guidelines for Intel® Agilex™ 7 Devices with F-Tile and R-Tile Transceivers
- Updated product family name to " Intel® Agilex™ 7".
- Retitled the document from Intel® Agilex™ Device Family Pin Connection Guidelines to Intel® Agilex™ 7 Device Family Pin Connection Guidelines.
|
| 2022.09.22 |
- Updated the connection guidelines of the VCCBAT pin.
- Updated the connection guidelines of the VCCL_HPS pin.
|
| 2022.09.06 |
Updated the connection guidelines of the VCCRCORE pin. |
| 2022.07.20 |
Updated the Optional/Dual-Purpose Configuration Pins section. |
| 2022.06.21 |
- Updated the connection guidelines of the VCCIO_PIO[3][A,B,C,D,E,F] pins.
- Updated the connection guidelines of the REFCLK_GXP[L10A,L10C]_CH[0,2][p,n] pins.
- Updated the connection guidelines of the I_PIN_PERST_N_GXF pin.
- Updated the VCCL_HPS power supply voltage for the –4X and –4F speed grades in the connection guidelines of the VCCL_HPS pin.
- Updated the following tables to include details on the –4X speed grade device for the VCCL_HPS and VCCPLLDIG_HPS:
- Table: Power Supply Sharing Guidelines for Intel® Agilex™ Devices with P-Tile and E-Tile Transceivers.
- Table: Power Supply Sharing Guidelines for Intel® Agilex™ Devices with F-Tile and R-Tile Transceivers.
- Added note (5) in Figure: Example Power Supply Sharing Guidelines for Intel® Agilex™ Devices with P-Tile and E-Tile Transceivers.
- Updated note (6) and added note (7) in Figure: Example Power Supply Sharing Guidelines for Intel® Agilex™ Devices with F-Tile and R-Tile Transceivers.
|
| 2022.04.20 |
Updated the connection guidelines of the REFCLK_FGT[L,R]_Q[2,3]_CH[8,9]P and REFCLK_FGT[L,R]_Q[2,3]_CH[8,9]N pins. |
| 2022.04.15 |
- Updated the connection guidelines of the VCCBAT pin.
- Removed the VCCBAT power supply from the following examples:
- Example 1—Power Supply Sharing Guidelines for Intel® Agilex™ Devices with P-Tile and E-Tile Transceivers
- Example 2—Power Supply Sharing Guidelines for Intel® Agilex™ Devices with F-Tile and R-Tile Transceivers
|
| 2022.01.14 |
Updated the pin description and connection guidelines of the NAND_RB pin. |
| 2021.11.08 |
- Added the Pins Status for Intel® Agilex™ Devices section.
- Updated the bank indexing of the following pins:
- CLK_[T,B]_2[A,B,C,D,E,F]_[0:1][p,n]
- CLK_[T,B]_3[A,B,C,D,E,F]_[0:1][p,n]
- PLL_[2][A,B,C,D,E,F]_[T,B]_FB[0:1]
- PLL_[3][A,B,C,D,E,F]_[T,B]_FB[0:1]
- PLL_[2][A,B,C,D,E,F]_[T,B]_CLKOUT[0:1][p,n]
- PLL_[3][A,B,C,D,E,F]_[T,B]_CLKOUT[0:1][p,n]
- DIFF_RX[2][A,B,C,D,E,F][1:24][p,n]
- DIFF_RX[3][A,B,C,D,E,F][1:24][p,n]
- DIFF_TX[2][A,B,C,D,E,F][1:24][p,n]
- DIFF_TX[3][A,B,C,D,E,F][1:24][p,n]
- Updated the pin description of the following pins:
- CLK_[T,B]_2[A,B,C,D,E,F]_[0:1][p,n]
- CLK_[T,B]_3[A,B,C,D,E,F]_[0:1][p,n]
- PLL_[2][A,B,C,D,E,F]_[T,B]_FB[0:1]
- PLL_[3][A,B,C,D,E,F]_[T,B]_FB[0:1]
- PLL_[2][A,B,C,D,E,F]_[T,B]_CLKOUT[0:1][p,n]
- PLL_[3][A,B,C,D,E,F]_[T,B]_CLKOUT[0:1][p,n]
- DIFF_RX[2][A,B,C,D,E,F][1:24][p,n]
- DIFF_RX[3][A,B,C,D,E,F][1:24][p,n]
- DIFF_TX[2][A,B,C,D,E,F][1:24][p,n]
- DIFF_TX[3][A,B,C,D,E,F][1:24][p,n]
- AVST_DATA[31:0]
- AVST_READY(3A bank)
- AVST_CLK(3A bank)
- AVST_VALID(3A bank)
- Updated the connection guidelines of the TCK pin.
- Updated the pin description of the nSTATUS pin.
- Updated the pin description and connection guidelines of the TEMPDIODE[1,3,4,6][p,n] pins.
- Updated the connection guidelines of the VCCH_SDM pin.
- Updated the connection guidelines of the VCCFUSEWR_SDM pin.
- Updated the connection guidelines of the REFCLK_GXE[R9A]_CH[0:8][p,n] pins.
- Updated the connection guidelines of the VCCH_GXP[L1,R1] pins.
- Updated the SDM_IO pins in the AVST x16 configuration scheme for the CONF_DONE and INIT_DONE signals in Table: SDM Optional Signal Pins.
- Updated the SDM_IO pins in the AVST x4, AVST x8, and AVST x32 configuration schemes for the nCATTRIP signal in Table: SDM Optional Signal Pins.
- Updated the VCCRCORE pin name.
- Updated the following pin names:
- RCOMP_P_FHT_GXF
- RCOMP_N_FHT_GXF
- RCOMP_P_Q2_CH1_FGT_GXF
- RCOMP_N_Q2_CH1_FGT_GXF
- Updated Figure: Example Power Supply Sharing Guidelines for Intel® Agilex™ Devices with F-Tile and R-Tile Transceivers to include a note for the VCCH_SDM rail.
- Removed the Appendix section.
|
| 2021.10.29 |
- Added note to the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals in Table: SDM Optional Signal Pins.
- Added new notes in the Notes to Intel® Agilex™ Device Family Pin Connection Guidelines section.
|
| 2021.07.02 |
- Added the nCATTRIP signal to Table: SDM Optional Signal Pins.
- Updated the connection guidelines of the VSIGP_[0,1] and VSIGN_[0,1] pins.
- Updated the connection guidelines of the REFCLK_GXE(L8,R9)_CH[0:8][p,n] pins.
|
| 2021.06.02 |
- Updated the IO_AUX_RREF(10,12,20,22), IO_AUX_RREF[10,12,20,22]_P, and U[10,12,20]_P_IO_RESREF_0 pin names.
- Updated the pin description of the IO_AUX_RREF(10,12,20,22), IO_AUX_RREF[10,12,20,22]_P, and U[10,12,20]_P_IO_RESREF_0 pins.
- Updated the connection guidelines of the VCCH_SDM pin.
- Updated the connection guidelines of the VCCH_FGT_GXF[L,R] and VCCERT_FGT_GXF[L,R] pins.
- Updated the connection guidelines of the I_PIN_PERST_N_GXF pin.
- Updated the supply tolerances of the VCCEHT_FHT_GXF and VCCERT_FGT_GXF pins in Table: Power Supply Sharing Guidelines for Intel® Agilex™ Devices with F-Tile and R-Tile Transceivers .
- Updated the VCCIO_PIO and VCCIO_PIO_SDM power rails in the following examples:
- Example 1—Power Supply Sharing Guidelines for Intel® Agilex™ Devices with P-Tile and E-Tile Transceivers
- Example 2—Power Supply Sharing Guidelines for Intel® Agilex™ Devices with F-Tile and R-Tile Transceivers
- Removed the pin description and connection guidelines of the IO_PLL_REFCLK_[12A,12C,13A,13C]_GXF pins.
- Removed F-series and I-series references.
|
| 2021.03.23 |
- Added the following sections:
- Intel® Agilex™ F-Tile Pins
- Intel® Agilex™ R-Tile Pins
- Appendix
- Updated Table: SDM Pins to include AS_nRST information for the SDM_IO15 pin.
- Updated the connection guidelines for the following pins in Table: Power Supply Pins:
- VCCIO_PIO_SDM
- VCCPT
- VCCR_CORE
- VCCH
- VCCIO_PIO[2][A,B,C,D] and VCCIO_PIO[3][A,B,C,D]
- Updated the connection guidelines for the VCC_HSSI_GXE(L1,R1) pins in Table: E-Tile Pins.
- Updated the LC filter reference for the VCCRT_GXE(L1,R1) pins to AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines.
- Updated the pin descriptions for the following pins in Table: P-Tile Pins:
- GXP[L10A,R11A]_RX_CH[19:0][p,n]
- GXP[L10A,R11A]_TX_CH[19:0][p,n]
- REFCLK_GXP[L10A,R11A]_CH[0,2][p,n]
- Updated Figure: Example Power Supply Sharing Guidelines for Intel® Agilex™ F-Series Devices with P-Tile and E-Tile Transceivers.
- Updated note (1) to add reference for the VCCL_HPS connection guidelines in the following figures:
- Power Supply Sharing Guidelines for Intel® Agilex™ F-Series Devices with P-Tile and E-Tile Transceivers
- Power Supply Sharing Guidelines for Intel® Agilex™ I-Series Devices with F-Tile and R-Tile Transceivers
- Power Supply Sharing Guidelines for Intel® Agilex™ ES Device (2486A)
- Removed the following sections:
- Intel® Agilex™ H-Tile Pins
- Example 2—Intel® Agilex™ (P-Tile and H-Tile)
- Removed SDM_IO15 from ASx4 configuration scheme for the following signals in Table: SDM Optional Signal Pins:
- CONF_DONE
- INIT_DONE
- CvP_CONFDONE
- SEU_ERROR
- HPS_COLD_nRESET
- Direct to Factory Image
|
| 2020.12.03 |
- Added the Intel® Agilex™ H-Tile Pins section.
- Added the following power supply sharing guidelines:
- Example 2—Intel® Agilex™ (P-Tile and H-Tile)
- Updated topic title Example 1—Intel® Agilex™ to Example 1—Intel® Agilex™ (P-Tile and E-Tile) for clarity.
- Updated the pin description for nCONFIG in Table: Dedicated Configuration/JTAG Pins—Preliminary.
- Updated the pin functions for all clock and PLL pins in Table: Clock and PLL Pins—Preliminary.
- Updated the pin functions and description in Table:Optional/Dual-Purpose Configuration Pins—Preliminary.
- Updated the pin descriptions for DIFF_RX and DIFF_TX in Table: Differential I/O Pins—Preliminary.
- Updated Table: Power Supply Pins—Preliminary:
- Updated the connection guidelines for VCCR_CORE and VCCA_PLL.
- Updated the connection guidelines for VCCL_HPS and VCCIO_PIO.
- Updated the connection guidelines for VCCIO_PIO[2][A,B,C,D] and VCCIO_PIO[3][A,B,C,D].
- Updated the pin description for VCCADC
- Updated the connection guidelines for VREFP_ADC, VREFN_ADC, VSIGP_[0,1], and VSIGN_[0,1] in Table: Voltage Sensor and Voltage Reference Pins—Preliminary.
- Updated Table: E-Tile Pins—Preliminary:
- Updated the supported I/O standards for GXE(L8,R9)_RX_CH[0:23][p,n] and GXE(L8,R9)_TX_CH[0:23][p,n] from CML –56G PAM4 and 30G NRZ to 57.8G PAM4 and 28.9G NRZ.
- Updated the pin description and connection guidelines of the REFCLK_GXE(L8,R9)(A,B,C)_CH[0:8][p,n] pins.
- Added a note in the P-Tile Pins section to include details on the lane reversal and polarity inversion on the PCB.
- Updated Table: HPS Supply Pins.
- Updated the notes for VCCR_CORE and VCCA_PLL to clarify the VCCR_CORE pin must be tied to a 1.8-V power supply for Intel® Agilex™ ES (2486A package) devices and 1.2-V power supply for Intel® Agilex™ production devices and other Intel® Agilex™ ES (except 2486A package) devices in the following tables and figures:
- Table: Power Supply Sharing Guidelines for Intel® Agilex™ Device with P-Tile and E-Tile Transceivers—Preliminary
- Table: Power Supply Sharing Guidelines for Intel® Agilex™ Device with P-Tile and H-Tile Transceivers—Preliminary
- Replaced references to Intel® Agilex™ Platform Design Guide with AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines for more details on decoupling recommendations for specific power rails.
|
| 2020.06.30 |
- Updated the connection guidelines of the TCK pin.
- Updated the pin description of the nSTATUS pin.
- Updated the pin description and connection guidelines of the nCONFIG pin.
- Updated the connection guidelines of the VCCIO_PIO_SDM pin.
- Updated the AVST x8, x16, and x32 configuration schemes for the Direct to Factory Image signal in the SDM Optional Signal Pins table.
- Removed the SDMMC_CFG configuration pin functions and connection guidelines from the Secure Device Manager (SDM) Pins table.
|
| 2020.05.05 |
Updated the connection guidelines of the VCCFUSEWR_SDM pin. |
| 2020.04.24 |
- Updated the voltage for VCCFUSEWR_SDM.
- Updated the connection guidelines of the VSIGP_[0,1] and VSIGN_[0,1] pins.
- Updated the pin function, pin description, and connection guidelines of the AVST_READY(3A bank) pin.
|
| 2020.02.04 |
Updated the connection guidelines of the VSIGP_[0,1] and VSIGN_[0,1] pins. |
| 2020.01.23 |
- Changed the Early Power Estimator (EPE) tool name to Intel® FPGA Power and Thermal Calculator.
- Updated the VCCPGM power supply to the VCCIO_SDM power supply in the connection guidelines of the TMS and TDI pins.
- Updated the pin description of the TCK, TMS, TDI, nSTATUS, nCONFIG, and OSC_CLK_1 pins.
- Updated the pin description of the AVST_DATA[31:0] and AVST_READY(3A bank) pins.
- Updated the pin names from SDM_MISSION_DATA[31:0], SDM_MISSION_CLK, and SDM_MISSION_DATA_VALID to AVST_DATA[31:0], AVST_CLK, and AVST_VALID.
- Updated pin name I_PIN_PERST_N_U[10,20]_P to I_PIN_PERST_N_P.
- Updated the I/O standard naming from 1.5V True Differential Signaling to True Differential Signaling.
- Updated supported I/O standard from SSTL 1.2V to 1.2V LVCMOS for the AVST_READY(3A bank), AVST_CLK(3A bank), and AVST_VALID(3A bank) pins.
- Updated the pin description of the DIFF_RX[2][A,B,C,D][1:24][p,n], DIFF_RX[3][A,B,C,D][1:24][p,n], DIFF_TX[2][A,B,C,D][1:24][p,n], and DIFF_TX[3][A,B,C,D][1:24][p,n] pins.
- Updated the resistor value from 2kΩ to 2.8kΩ for the IO_AUX_RREF[10,20]_P pins.
- Updated the pin description and connection guidelines of the VCCBAT pin.
- Updated the pin description and connection guidelines of the VCCPT pin.
- Updated the pin description and connection guidelines of the VCCR_CORE pin.
- Updated the pin description of the VCCA_PLL pin.
- Updated the connection guidelines of the DNU pins.
- Updated the connection guidelines of the VCCIO_SDM pin.
- Updated the pin function of the RREF_SDM pin.
- Updated the pin description and connection guidelines of the REFCLK_GXE(L8,R9)_CH[0:8][p,n] pins.
- Updated the connection guidelines of the GXP[L10A,R11A]_RX_CH[19:0][p,n] pins.
- Updated the connection guidelines of the GXP[L10A,R11A]_TX_CH[19:0][p,n] pins.
- Updated the connection guidelines of the REFCLK_GXP[L10A,R11A]_CH[0,2][p,n] pins.
- Updated the resistor value from 200Ω to 169Ω of the U[10,20]_P_IORESREF_0 pins.
- Updated the connection guidelines of the I_PIN_PERST_P pins.
- Updated the connection guidelines of the VCCL_HPS pin.
- Updated Table: Power Supply Sharing Guidelines for Intel® Agilex™ Device.
- Updated Figure: Example Power Supply Sharing Guidelines for Intel® Agilex™ Device.
- Added SDM_IO8 to AVST x16 and x32 for the CONF_DONE and INIT_DONE pins.
- Added reference to the External Memory Interface Pin Information for Intel® Agilex™ Devices in the External Memory Interface Pins section.
- Added reference to the E-Tile Transceiver PHY User Guide in the E-Tile Pins section.
|
| 2019.06.10 |
Initial release. |