Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 11/07/2022

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1.7.3. Running Gate-Level Simulation (NativeLink Flow)

To run gate-level simulation with the NativeLink flow, follow these steps:
  1. Prepare for simulation.
  2. Set up the simulation environment. To generate only a functional (rather than timing) gate-level netlist, click More EDA Netlist Writer Settings, and turn on Generate netlist for functional simulation only.
  3. To synthesize the design, follow one of these steps:
    • To generate a post-fit functional or post-fit timing netlist and then automatically simulate your design according to your NativeLink settings, Click Processing > Start Compilation. Skip to step 6.
    • To synthesize the design for post-synthesis functional simulation only, click Processing > Start > Start Analysis and Synthesis.
  4. To generate the simulation netlist, click Start EDA Netlist Writer.
  5. Click Tools > Run Simulation Tool > Gate Level Simulation.
  6. Review and analyze the simulation results in your simulator. Correct any unexpected or incorrect conditions found in your design. Simulate the design again until you verify correct behavior.