ID 683080
Date 11/07/2022
Public

## 4.3.1. Elaborating Your Design

The simulator automatically reads the .sdo file during elaboration of the Intel® Quartus® Prime-generated Verilog HDL or SystemVerilog HDL netlist file. The ncelab command recognizes the embedded system task $sdf_annotate and automatically compiles and annotates the .sdo file by running ncsdfc automatically. VHDL netlist files do not contain system task calls to locate your .sdf file; therefore, you must compile the standard .sdo file manually. Locate the .sdo file in the same directory where you run elaboration or simulation. Otherwise, the$sdf_annotate task cannot reference the .sdo file correctly. If you are starting an elaboration or simulation from a different directory, you can either comment out the \$sdf_annotate and annotate the .sdo file with the GUI, or add the full path of the .sdo file.

Note: If you use NC-Sim for post-fit VHDL functional simulation of a Stratix® V design that includes RAM, an elaboration error might occur if the component declaration parameters are not in the same order as the architecture parameters. Use the -namemap_mixgen option with the ncelab command to match the component declaration parameter and architecture parameter names.

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