Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 11/07/2022

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3.2.3. Generating Power Analysis Files

You can generate a Verilog Value Change Dump File (.vcd) for power analysis in the Intel® Quartus® Prime software, and then run the .vcd from the VCS software. Use this .vcd for power analysis in the Intel® Quartus® Prime power analyzer.

To generate and use a .vcd for power analysis, follow these steps:

  1. In the Intel® Quartus® Prime software, click Assignments > Settings.
  2. Under EDA Tool Settings, click Simulation.
  3. Turn on Generate Value Change Dump file script, specify the type of output signals to include, and specify the top-level design instance name in your testbench.
  4. Click Processing > Start Compilation.
  5. Use the following command to include the script in your testbench where the design under test (DUT) is instantiated:
    include <revision_name>_dump_all_vcd_nodes.v
    Note: Include the script within the testbench module block. If you include the script outside of the testbench module block, syntax errors occur during compilation.
  6. Run the simulation with the VCS command. Exit the VCS software when the simulation is finished and the <revision_name> .vcd file is generated in the simulation directory.