Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 11/07/2022

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3.2.2. Disabling Timing Violation on Registers

In certain situations, you may want to ignore timing violations on registers and disable the “X” propagation that occurs. For example, this technique may be helpful to eliminate timing violations in internal synchronization registers in asynchronous clock-domain crossing. Intel® Arria® 10 devices do not support timing simulation. Intel® Arria® 10 devices do not support timing simulation.

By default, the x_on_violation_option logic option is enabled for all design registers, resulting in an output of “X” at timing violation. To disable “X” propagation at timing violations on a specific register, disable the x_on_violation_option logic option for the specific register, as shown in the following example from the Intel® Quartus® Prime Settings File (.qsf).

set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to \ <register_name>