Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 11/07/2022
Document Table of Contents

4.3. Cadence Incisive Enterprise (IES) Guidelines

The following guidelines apply to simulation of Intel FPGA designs in the IES software:
  • Do not specify the -v option for because it defines a systemverilog package.
  • Add -verilog and +verilog2001ext+.v options to make sure all Verilog HDL files are compiled as verilog 2001 files, and all other files are compiled as systemverilog files.
  • Add the -lca option for Stratix® V and later families because they include IEEE-encrypted simulation files for IES.
  • Add -timescale=1ps/1ps to ensure picosecond resolution.

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