Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation
ID
683080
Date
11/07/2022
Public
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1.1. Simulator Support
1.2. Simulation Levels
1.3. HDL Support
1.4. Simulation Flows
1.5. Preparing for Simulation
1.6. Simulating Intel® FPGA IP Cores
1.7. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition)
1.8. Running a Simulation (Custom Flow)
1.9. Simulating Intel FPGA Designs Revision History
2.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries
2.2.2. Disabling Timing Violation on Registers
2.2.3. Passing Parameter Information from Verilog HDL to VHDL
2.2.4. Increasing Simulation Speed in ModelSim and Questa Simulators
2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays
2.2.6. Viewing Simulation Messages
2.2.7. Generating Power Analysis Files
2.2.8. Viewing Simulation Waveforms
2.2.9. Simulating with Questa* Intel® FPGA Edition Waveform Editor
4.2. Using GUI or Command-Line Interfaces
To start the GUI, type nclaunch at a command prompt.
Program | Function |
---|---|
ncvlog | ncvlog compiles your Verilog HDL code and performs syntax and static semantics checks. |
ncvhdl |
ncvhdl compiles your VHDL code and performs syntax and static semantics checks. |
ncelab | Elaborates the design hierarchy and determines signal connectivity. |
ncsdfc | Performs back-annotation for simulation with VHDL simulators. |
ncsim | Runs mixed-language simulation. This program is the simulation kernel that performs event scheduling and executes the simulation code. |