Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 11/07/2022

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Document Table of Contents

4.1. Quick Start Example (NC-Verilog)

You can adapt the following RTL simulation example to get started quickly with IES:
  1. Click View > TCL Console to open the TCL Console.
  2. To specify your EDA simulator and executable path, type the following Tcl package command in the Intel® Quartus® Prime tcl shell window:
    set_user_option -name EDA_TOOL_PATH_NCSIM <ncsim executable path>
    set_global_assignment -name EDA_SIMULATION_TOOL "NC-Verilog (Verilog)"
  3. Compile simulation model libraries using one of the following methods:
    • Run NativeLink RTL simulation to compile required design files, simulation models, and run your simulator. Verify results in your simulator. If you complete this step you can ignore the remaining steps.
    • To automatically compile all required simulation model libraries for your design in your supported simulator, click Tools > Launch Simulation Library Compiler. Specify options for your simulation tool, language, target device family, and output location, and then click OK.
    • You can also compile Intel FPGA simulation libraries from the command-line:
      quartus_sh --simlib_comp -tool ncsim -family <device family>
        -language <language> -gen_only -cmd_file <sim_script_file_name>
      This generates the cds.lib, hdl.var and, <sim_script_file_name>, which can be used to compile the simulation libraries.

    Use the compiled simulation model libraries during simulation of your design. Refer to your EDA simulator's documentation for information about running simulation.

  4. Elaborate your design and testbench with IES:
    ncelab <work library>.<top-level entity name>
  5. Run the simulation:
    ncsim <work library>.<top-level entity name>