Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

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ID 683080
Date 11/07/2022
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Document Table of Contents
Document Table of Contents x
1. Simulating Intel FPGA Designs 2. Questa* Intel® FPGA Edition, ModelSim® , and Questa* Simulator Support 3. Synopsys VCS* and VCS MX Support 4. Cadence Simulator Support 55.4. Aldec Active-HDL* and Riviera-PRO* Support A. Intel® Quartus® Prime Standard Edition User Guides
1. Simulating Intel FPGA Designs x
1.1. Simulator Support 1.2. Simulation Levels 1.3. HDL Support 1.4. Simulation Flows 1.5. Preparing for Simulation 1.6. Simulating Intel® FPGA IP Cores 1.7. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.8. Running a Simulation (Custom Flow) 1.9. Simulating Intel FPGA Designs Revision History
1.5. Preparing for Simulation x
1.5.1. Compiling Simulation Models
1.6. Simulating Intel® FPGA IP Cores x
1.6.1. Generating IP Simulation Files
1.6.1. Generating IP Simulation Files x
1.6.1.1. Generating IP Functional Simulation Models ( Intel® Quartus® Prime Standard Edition)
1.7. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) x
1.7.1. Setting Up NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.7.2. Running RTL Simulation (NativeLink Flow) 1.7.3. Running Gate-Level Simulation (NativeLink Flow)
2. Questa* Intel® FPGA Edition, ModelSim® , and Questa* Simulator Support x
2.1. Quick Start Example (ModelSim with Verilog) 2.2. Questa* Intel® FPGA Edition, ModelSim, and Questa Simulator Guidelines 2.3. ModelSim Simulation Setup Script Example 2.4. Unsupported Features 2.5. Questa* Intel® FPGA Edition, ModelSim® , and Questa* Simulator Support Revision History
2.2. Questa* Intel® FPGA Edition, ModelSim, and Questa Simulator Guidelines x
2.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries 2.2.2. Disabling Timing Violation on Registers 2.2.3. Passing Parameter Information from Verilog HDL to VHDL 2.2.4. Increasing Simulation Speed in ModelSim and Questa Simulators 2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays 2.2.6. Viewing Simulation Messages 2.2.7. Generating Power Analysis Files 2.2.8. Viewing Simulation Waveforms 2.2.9. Simulating with Questa* Intel® FPGA Edition Waveform Editor
3. Synopsys VCS* and VCS MX Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS and VCS MX Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Synopsys VCS* and VCS MX Support Revision History
3.2. VCS and VCS MX Guidelines x
2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays 3.2.2. Disabling Timing Violation on Registers 3.2.3. Generating Power Analysis Files
4. Cadence Simulator Support x
4.1. Quick Start Example (NC-Verilog) 4.2. Using GUI or Command-Line Interfaces 4.3. Cadence Incisive Enterprise (IES) Guidelines 4.4. IES Simulation Setup Script Example 4.5. Cadence Simulator Support Revision History
4.3. Cadence Incisive Enterprise (IES) Guidelines x
4.3.1. Elaborating Your Design 4.3.2. Back-Annotating Simulation Timing Data (VHDL Only) 4.3.3. Disabling Timing Violation on Registers 4.3.4. Simulating Pulse Reject Delays 4.3.5. Viewing Simulation Waveforms
55.4. Aldec Active-HDL* and Riviera-PRO* Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 55.4. Aldec Active-HDL* and Riviera-PRO* Support
5.2. Aldec Active-HDL and Riviera-PRO Guidelines x
5.2.1. Compiling SystemVerilog Files 2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays 5.2.3. Disabling Timing Violation on Registers
1. Simulating Intel FPGA Designs
2. Questa* Intel® FPGA Edition, ModelSim® , and Questa* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Cadence Simulator Support
55.4. Aldec Active-HDL* and Riviera-PRO* Support
A. Intel® Quartus® Prime Standard Edition User Guides

1.8. Running a Simulation (Custom Flow)

Use a custom simulation flow to support any of the following more complex simulation scenarios:
  • Custom compilation, elaboration, or run commands for your design, IP, or simulation library model files (for example, macros, debugging/optimization options, simulator-specific elaboration or run-time options)
  • Multi-pass simulation flows
  • Flows that use dynamically generated simulation scripts

Use these to compile libraries and generate simulation scripts for custom simulation flows:

  • NativeLink-generated scripts—use NativeLink only to generate simulation script templates to develop your own custom scripts.
  • Simulation Library Compiler—compile Intel FPGA simulation libraries for your device, HDL, and simulator. Generate scripts to compile simulation libraries as part of your custom simulation flow. This tool does not compile your design, IP, or testbench files.
  • IP and Platform Designer (Standard) simulation scripts—use the scripts generated for Intel FPGA IP cores and Platform Designer (Standard) systems as templates to create simulation scripts. If your design includes multiple IP cores or Platform Designer (Standard) systems, you can combine the simulation scripts into a single script, manually or by using the
ip-make-simscript utility.

Use the following steps in a custom simulation flow:

  1. Use the EDA Netlist Writer (quartus_eda) to generate the design netlist and other output files for use with other EDA tools.
  2. Compile the design and testbench files in your simulator.
  3. Run the simulation in your simulator.

Post-synthesis and post-fit gate-level simulations run significantly slower than RTL simulation. Intel FPGA recommends that you verify your design using RTL simulation for functionality and use the Timing Analyzer for timing. Timing simulation is not supported for Arria® V, Cyclone® V, Stratix® V, and newer families.

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