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1.1. Simulator Support
1.2. Simulation Levels
1.3. HDL Support
1.4. Simulation Flows
1.5. Preparing for Simulation
1.6. Simulating Intel® FPGA IP Cores
1.7. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition)
1.8. Running a Simulation (Custom Flow)
1.9. Simulating Intel FPGA Designs Revision History
2.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries
2.2.2. Disabling Timing Violation on Registers
2.2.3. Passing Parameter Information from Verilog HDL to VHDL
In-line Parameter Passing Example
2.2.4. Increasing Simulation Speed in ModelSim and Questa Simulators
2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays2.2.53.2.15.2.2. Simulating Transport Delays
2.2.6. Viewing Simulation Messages
2.2.7. Generating Power Analysis Files
2.2.8. Viewing Simulation Waveforms
2.2.9. Simulating with Questa* Intel® FPGA Edition Waveform Editor
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2.2.3. Passing Parameter Information from Verilog HDL to VHDL
You must use in-line parameters to pass values from Verilog HDL to VHDL.
By default, the x_on_violation_option logic option is enabled for all design registers, resulting in an output of “X” at timing violation. To disable “X” propagation at timing violations on a specific register, disable the x_on_violation_option logic option for the specific register, as shown in the following example from the Intel® Quartus® Prime Settings File (.qsf).
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to \ <register_name>
In-line Parameter Passing Example
lpm_add_sub#(.lpm_width(12), .lpm_direction("Add"), .lpm_type("LPM_ADD_SUB"), .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO" )) lpm_add_sub_component ( .dataa (dataa), .datab (datab), .result (sub_wire0) );
Note: The sequence of the parameters depends on the sequence of the GENERIC in the VHDL component declaration.