5.1. Signal Sensing in Sigma-Delta and MAX 10 Integrated ADCs
Each Intel® MAX® 10 ADC submodule converts the 8 input channels in sequence. The Intel® MAX® 10 ADC Qsys component configures the sequence. Intel chooses the order in which the design connects signals to the ADC inputs. Also, Intel chooses the sequence in the Qsys component to minimize the time difference between the most recent feedback current samples for motor control.
Sigma-delta modulators on the power board convert analog signals to a one-wire digital bitstream. The design demodulates or filters the bitstream in the FPGA. The FPGA uses two types of sigma-delta filter IP in the FPGA, ADC modules and DC link modules, each with different scaling and offset.
The design downloads and filters all sigma delta inputs in parallel so no skew exists between the samples that it feeds to the software application.
Each ADC type has a different input and output ranges with the corresponding 'C' data type..
|ADC Type||Input Range||Count Range||C Data type|
|Sigma-delta ADC||-320…+320mV||-32768…+32767||Signed 16-bit|
|Sigma-delta DC link||0…+320mV||0…+32767||Unsigned 16-bit|
|MAX 10||0…2.5V||0…4097||Unsigned 16-bit|
The input current and DC bus current are only available via sigma-delta ADCs.
Position feedback samples are scaled to a 23 bit unsigned integer, for consistency across all encoder types supported by this and previous Drive-On-Chip reference designs.
|Feedback Quantity||Sigma Delta Interface IP||Sigma Delta Scaling for Tandem Motion Power Board||Intel® MAX® 10 Scaling for Tandem Motion Power Board|
|Motor Phase Voltages||ADC interface||545 counts/V||67.7 counts/V|
|DC Bus Voltage||ADC interface||40 counts/V||67.7 counts/V|
|Input Voltage||DC Link||895 counts/V||223 counts/V|
|Input Current||DC Link||256 counts/A||N/A|
|DC-DC Inductor Current||ADC interface||717 counts/A||57.3 counts/A|
|DC Bus Current||DC Link||1638 counts/A||N/A|
|Motor Phase Currents||ADC interface||1024 counts/A||81.9 counts/A|
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