AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

ID 683072
Date 7/26/2023
Public
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4.2. Generating the Qsys System

After making any changes in the Qsys project for the Drive-On-Chip Design Example, generate the system.
  1. In Qsys click File > Save.
  2. Click Generate HDL….
  3. Click Generate.
  4. Click Close.
  5. If your changes result in new exported connections you can view the Qsys component template by clicking Generate > Show Instantiation Template….
    Add new ports to the Qsys component instantiation in the top level RTL of the project <project variant>.v.
  6. Close Qsys .
After making a change to the Qsys system you must:
  • Regenerate the Nios II BSP and rebuild the software
  • Compile the hardware