AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

ID 683072
Date 4/22/2021
Public
Document Table of Contents

7.11.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs

The top-level model is a simple dummy testbench with constant inputs of the correct arithmetic types to control hardware generation, which includes the FOC algorithm model.
Figure 42. DSP Builder for Intel FPGAs Model

The FOC algorithm comprises the FOC algorithm block and a latch block for implementing the integrators necessary for the PI controllers in the FOC algorithm. DSP Builder for Intel FPGAs implements the latches outside because of limitations of the folding synthesis.

The design includes fixed-point and floating-point models that implement the FOC algorithm.

Each model calls a corresponding .m setup script during initialization to set up the arithmetic precision, folding factor, and target clock speed. The folding factor is set to a large value to minimize resource usage.

Table 15.  Default settings in Setup Script
Model Folding Factor Clock Speed (MHz) Input Precision Output Precision
Fixed point 500 100 sfix16En10 sfix32En10
Floating point 500 100 sfix32En10 sfix32En10

The following models generate the FOC block including the Avalon memory-mapped interface:

  • DF_float_alu_av.slx for floating-point designs
  • DF_fixp16_alu_av.slx for fixed-point designs

Verification models stimulate the FOC algorithm using dynamically changing inputs:

  • verify_DF_float_alu.slx
  • verify_DF_fixp16_alu.slx

Closed-loop simulation models validate that the FOC correctly controls a motor in simulation:

  • sim_DF_float_alu.slx
  • sim_DF_fixp16_alu.slx

A Simulink* library model contains the main FOC algorithm code, which the other models refer to:

  • foc_blocks.slx

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