AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

ID 683072
Date 4/22/2021
Public
Document Table of Contents

7. Functional Description of the Drive-On-Chip Design Example for Intel® MAX® 10 Devices

The design consists of two main elements: Qsys, DSP Builder for Intel FPGAs, IP, and RTL sources compiled into an FPGA programming file; and C source code compiled to run on a Nios II processor in the FPGA.

The Qsys system consists of:

  • Nios® II processor subsystem
  • DC link monitors
  • Intel® MAX® 10 modular dual ADC
  • DC-DC converter
  • FOC subsystem
  • One or two motor drive axes comprising the following motor control peripheral components:
    • 6-channel PWM
    • Drive system monitor
    • Quadrature encoder interface
    • Resolver SPI interface
    • ADC interface
Figure 22. Qsys System Top-Level Design
Figure 23. Qsys System for a Drive Axis
Figure 24. Qsys System for DC-DC Converter

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