AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

Download PDF
ID 683072
Date 7/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices 3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 5. About the Scaling of Feedback Signals 6. Motor Control Software 7. Functional Description of the Drive-on-Chip Design Example 8. Achieving Timing Closure on a Motor Control Design 9. Design Security Recommendations 10. Reference Documents for the Drive-on-Chip Design Example 11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.1. Software Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up the Motor Control Board with your Development Board for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.5. Importing the Drive-On-Chip Design Example Software Project 3.6. Configuring the FPGA Hardware for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.7. Programming the Nios II Software to the Device for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.8. Applying Power to the Power Board 3.9. Debugging and Monitoring the Drive-On-Chip Design Example with System Console 3.10. System Console GUI Upper Pane for the Drive-On-Chip Design Example 3.11. System Console GUI Lower Pane for the Drive-On-Chip Design Example 3.12. Controlling the DC-DC Converter 3.13. Tuning the PI Controller Gains 3.14. Controlling the Speed and Position Demonstrations 3.15. Monitoring Performance
3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.2.1. Preparing the Rechargeable Battery
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
4.1. Changing the Intel® MAX® 10 ADC Thresholds or Conversion Sequence 4.2. Generating the Qsys System 4.3. Compiling the Hardware in the Intel Quartus Prime Software 4.4. Generating and Building the Nios II BSP for the Drive-On-Chip Design Example 4.5. Software Application Configuration Files 4.6. Compiling the Software Application for the Drive-On-Chip Design Example 4.7. Programming the Design into Flash Memory
4.5. Software Application Configuration Files x
4.5.1. Defining a New Motor or Encoder Type
5. About the Scaling of Feedback Signals x
5.1. Signal Sensing in Sigma-Delta and MAX 10 Integrated ADCs 5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 5.3. Scale Factors for the Drive-on-Chip Design Example in the System Console Toolkit
6. Motor Control Software x
6.1. Viewing Motor Control Software Help Files
7. Functional Description of the Drive-on-Chip Design Example x
7.1. Processor Subsystem 7.2. Six-channel PWM Interface 7.3. DC Link Monitor 7.4. Drive System Monitor 7.5. Quadrature Encoder Interface 7.6. Sigma-Delta ADC Interface for Drive Axes 7.7. Intel® MAX® 10 ADCs 7.8. ADC Threshold Sink 7.9. DC-DC Converter 7.10. Motor Control Modes 7.11. FOC Subsystem 7.12. DEKF Technique 7.13. Signals 7.14. Registers
7.4. Drive System Monitor x
7.4.1. Drive System Monitor States for the Drive-on-Chip Design Example
7.6. Sigma-Delta ADC Interface for Drive Axes x
7.6.1. Offset Adjustment for Sigma-Delta ADC Interface
7.9. DC-DC Converter x
7.9.1. DC-DC Control Simulink Models 7.9.2. Sigma-Delta ADC Interface for DC-DC Converter
7.9.1. DC-DC Control Simulink Models x
7.9.1.1. DC-DC Control Block 7.9.1.2. Generating VHDL for the DSP Builder for Intel FPGAs Models for the DC-DC Converter
7.9.1.1. DC-DC Control Block x
7.9.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format
7.11. FOC Subsystem x
7.11.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs 7.11.2. Avalon Memory-Mapped Interface 7.11.3. About DSP Builder for Intel FPGAs 7.11.4. DSP Builder for Intel FPGAs Folding 7.11.5. DSP Builder for Intel FPGAs Model Resource Usage 7.11.6. DSP Builder for Intel FPGAs Design Guidelines 7.11.7. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
8. Achieving Timing Closure on a Motor Control Design x
8.1. Optimizing Motor Control Designs
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example
8. Achieving Timing Closure on a Motor Control Design
9. Design Security Recommendations
10. Reference Documents for the Drive-on-Chip Design Example
11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices

7.14. Registers

The Drive-on-Chip Design Example contains many registers that you can set.
Table 27.  Six-Channel PWM Interface Control and Status RegistersWrite reserved bits as zero and read as zero.
Address Name Bits Description Reset Value Access
0x00 - - Reserved - -

0x04

pwm_u

 [31:15] Reserved - -
[14:0] phase U PWM switching threshold in PWM clocks 0x0 RW

0x08

pwm_v

 [31:15] Reserved - -
[14:0] phase V PWM switching threshold threshold in PWM clocks 0x0 RW

0x0C

pwm_w

 [31:15] Reserved - -
[14:0] phase W PWM switching threshold threshold in PWM clocks 0x0 RW

0x10

max

 [31:15] Reserved - -
[14:0] PWM maximum count threshold in PWM clocks 0x0 RW

0x14

block

 [31:8] Reserved - -
[7:0] PWM blocking (dead time) register threshold in PWM clocks 0x0 RW

0x18

trigger_up

 [31:15] Reserved - -
[14:0] PWM up count trigger for ADC threshold in PWM clocks 0x0 RW

0x1C

trigger_down

 [31:15] Reserved - -
[14:0] PWM down count trigger for ADC threshold in PWM clocks 0x0 RW

0x20

pwm_direct_interface

 [31:1] Reserved - -
[1:0] PWM direct interface control, 1 for direct interface, 0 for Avalon interface 0x0 RW
0x24 to 0x28 Reserved [31:0] Reserved - -

0x2C

pwm_hall_en

 [31:3] Reserved - -
[3:0] PWM hall enable 0x0 RW
Table 28.  DC Link Monitor Interface Control and Status RegistersWrite reserved bits as zero and read as zero.
Address Name Bits Description Reset Value Access
0x00 - - Reserved - -
0x04 offset [31:16] Reserved - -
[15:0] Offset. A value of 16384 corresponds to a zero offset. 0x0 RW

0x08

 k_64 [31:1] Reserved - -
[0] sinc3 filter decimation rate. When set to 0, the sinc3 decimation rate is M=64; when set to 1, the sinc3 decimation rate is M=128. 0x0 RW

0x0C

 ref_disable [31:16] Reserved - -
[15:0] DC-link voltage disable level. This register provides the maximum allowable voltage for link voltage. If the maximum value is exceeded the overvoltage output is driven, to shut down the system. 0x0 RW

0x10

 link_ref [31:16] Reserved - -
[15:0] DC-link chopper voltage level. The chopper IGBT transistor is turned on when the DC-link voltage exceeds this value. 0x0 RW

0x14

 bottom_ref [31:16] Reserved - -
[15:0] DC-link undervoltage reference level. If the link voltage falls below the reference level the undervoltage output is driven. 0x0 RW

0x18

 brake_t [31:11] Reserved - -
[10:0] This register is not used. 0x0 RW

0x1C

 brake_max_level [31:16] Reserved - -
[15:0] This register is not used. 0x0 RW

0x20

 dc_link [31:16] Reserved - -
[15:0] Current link voltage reading 0x0 R
0x24 brake_level [31:16] Reserved - -
[15:0] This register is not used. 0x0 R

0x28

status

 [31:3] Reserved - -
[2] DC link overvoltage status 0x0 R
[1] DC link undervoltage status 0x0 R
[0] Chopper gate signal status 0x0 R
Table 29.  Drive System Monitor Control and Status RegistersWrite reserved bits as zero and read as zero. R/W1C bits are read, write a 1 to clear the bit
Address Name Bits Description Reset Value Access
0x00 control [31:3] Reserved - -
[2:0] Control. Write to this register to request a change of state in the drive system monitor. 0x0 RW
0x04 status [31:12] Reserved - -
[11:9] Current DSM state. 0x0 R
[8] PWM control, upper PWM enable - -
[7] PWM control, lower PWM enable 0x0 R
[6] PWM control, PWM enable - -
[4] IGBT error 0x0 R/W1C
[3] ADC clock status - R/W1C
[2] Undervoltage status 0x0 R/W1C
[1] Overvoltage status - R/W1C
[0] Overcurrent status 0x0 R/W1C
Table 30.  Quadrature Encoder Interface Control and Status RegistersWrite reserved bits as zero and read as zero.
Address Name Bits Description Reset Value Access
0x00 control [31:3] Reserved. - -
[2] direction bit. Reverses the count direction when set. 0x0 RW
[1] index_reset_en bit. Count will reset on index pulse if this bit is set. 0x0 RW
[0] index_capture_en bit. Count will be captured in index capture reg, when index pulse occurs, if this bit is set. 0x0 RW
0x04 count capture [31:0] Captures current count on each strobe. 0x0 R
0x08 maximum count [31:0] Maximum count. Count will reset to zero when it reaches this value. 0x3FFF RW
0x0C count [31:0] Current count value. 0x0 RW
0x10 index capture [31:0] Captures current count when index pulse occurs if index_capture_en bit is set. 0x0 R
Table 31.  Sigma-Delta ADC Interface Control and Status RegistersWrite reserved bits as zero and read as zero.
Address Name Bits Description Reset Value Access
0x0 - - Reserved - -
0x04 offset_u [31:16] Reserved. - -
[15:0] Offset for phase U. A value of 32,768 corresponds to 0 offset. 0x0 RW
0x08 offset_w [31:16] Reserved. - -
[15:0] Offset for phase W. A value of 32,768 corresponds to 0 offset. 0x0 RW
0x0C i_peak [31:10] Reserved. - -
[9:0] Overcurrent detection threshold. 0x0 RW
0x10 d [31:3] Reserved. - -
[2] sinc3 filter decimation rate. When set to 0, the sinc3 decimation rate is M=128 for the control loop and M=16 for overcurrent detection; when set to 1, the sinc3 decimation rate is M=64 for the control loop and M=8 for the overcurrent detection. 0x0 RW
[1] Overcurrent enable 0x0 RW
[0] Overvoltage enable 0x0 RW
0x14 irq_ack [31:1] Reserved. - -
[0] 0x0 W1C
0x18 status [31:5] Reserved. - -
[4] 0x0 R
[3] 0x0 R
[2] Overcurrent for phase U 0x0 R
[1] Overcurrent for phase W 0x0 R
[0] Overcurrent for any phase 0x0 R
0x1C i_u [31:10] Reserved. - -
[9:0] Current in phase U. 0x0 R
0x20 i_w [31:10] Reserved. - -
[9:0] Current in phase W. 0x0 R
0x24 i_peak [31:10] Reserved. - -
[9:0] Overcurrent detection threshold. 0x0 RW
0x28 i_v [31:10] Reserved. - -
[9:0] Current in phase V. 0x0 R
0x2C offset_v [31:16] Reserved. - -
[15:0] Offset for phase V. A value of 32,768 corresponds to 0 offset. 0x0 RW
0x30 Overcurrent_u [31:10] Reserved. - -
[9:0] Overcurrent value for phase U 0x0 R
0x34 Overcurrent_v [31:10] Reserved. - -
[9:0] Overcurrent value for phase V 0x0 R
0x38 Overcurrent_w [31:10] Reserved. - -
[9:0] Overcurrent value for phase W 0x0 R
0x3C Set IRQ counter [31:3] Reserved. - -
[2:0] IRQ counter to ensure enough IRQ timing, autocalculated in the software.

0x0

RW
Table 32.  MAX10 ADC Threshold Sink Control and Status RegistersWrite reserved bits as zero and read as zero
Address Name Bits Description Reset Value Access
0x00 capture under enable [31:16] Reserved. - -
[15:0] Enable latching of under threshold errors. One bit per ADC channel. 0 RW
0x04 capture over enable [31:16] Reserved. - -
[15:0] Enable latching of over threshold errors. One bit per ADC channel. 0 RW
0x08 output under enable [31:16] Reserved. - -
[15:0] Enable output of under threshold errors. One bit per ADC channel. 0 RW
0x0C output over enable [31:16] Reserved. - -
[15:0] Enable output of over threshold errors. One bit per ADC channel. 0 RW
0x10 latch under [31:16] Reserved. - -
[15:0] Latched under threshold errors. One bit per ADC channel. 0 R
0x14 latch over [31:16] Reserved. - -
[15:0] Latched over threshold errors. One bit per ADC channel. 0 R
0x18 output under [31:16] Reserved. - -
[15:0] Under threshold output status. One bit per ADC channel. 0 R
0x1C output over [31:16] Reserved. - -
[15:0] Over threshold output status. One bit per ADC channel. 0 R
0x20 set under error [31:16] Reserved. - -
[15:0] Set under threshold errors. One bit per ADC channel. Write 1s to set error bits. 0 W1S
0x24 set over error [31:16] Reserved. - -
[15:0] Set over threshold errors. One bit per ADC channel. Write 1s to set an error bits. 0 W1S
0x28 clear under error [31:16] Reserved. - -
[15:0] Clear under threshold errors. One bit per ADC channel. Write 1s to clear error bits. 0 W1C
0x2C clear over error [31:16] Reserved. - -
[15:0] Clear over threshold errors. One bit per ADC channel. Write 1s to clear error bits. 0 W1C
Table 33.  DC-DC Converter Control and Status RegistersWrite reserved bits as zero and read as zero
Address Name Bits Description Reset Value Access

0x00

control

 [31:5] Reserved - -
[4] State of REGEN_EN signal from the power board - R
[3] Reserved - -
[2]

Enable regeneration

0 RW
[1] Enable closed loop mode 0 RW
[0] Enable Dc-DC gated with enable_in input 0 RW

0x04

cmd_dc

 [31:14] Reserved - -
[13:0] Commanded DC-DC output level in 1V increments 0 RW

0x08

 fault_reg [31:6] Reserved - -
[5] Input overvoltage detected 0 RW
[4] Input undervoltage detected 0 RW
[3] Output overvoltage detected 0 RW
[2] Output undervoltage detected 0 RW
[1] Input overcurrent detected 0 RW
[0] Output overcurrent detected 0 RW
0x0C - - Reserved 0 -

0x10

duty

 [31:14] Reserved - -
[13:0] Duty cycle for open loop mode, 0 – 100 50 RW

0x14

freq

 [31:14] Reserved - -
[13:0] Frequency of operation, kHz 64 RW

0x18

-

 - Reserved - -

0x1C

 - - Reserved - -

0x20

fb_current_a

 [31:13] Reserved - -
[12:0] Phase 0 current feedback sample, 100 = 1A 0 RW

0x24

fb_current_b

 [31:13] Reserved - -
[12:0] Phase 1current feedback sample, 100 = 1A 0 RW

0x28

fb_voltage

 [31:13] Reserved - -
[12:0] DC-DC output voltage feedback sample, 40 = 1V 0 RW
0x2C - - Reserved 0 -
0x30 offset_fb_current_a [31:16] Reserved - -
[15:0] Phase 0 current feedback ADC offset 0x8000 RW
0x34 offset_fb_current_b [31:16] Reserved - -
[15:0] Phase 1 current feedback ADC offset 0x8000 RW
0x38 offset_fb_voltage [31:16] Reserved - -
[15:0] DC-DC output voltage feedback ADC offset 0x8000 RW
0x3C - - Reserved 0 -

0x40

pgain_voltage

 [31:14] Reserved - -
[13:0]

P gain coefficient for voltage control loop * 100

[AC TODO] resolution? Scale?

300 RW

0x44

igain_voltage

 [31:14] Reserved - -
[13:0] I gain coefficient for voltage control loop * 1e-7 (1/avs_clk) 4000 RW

0x48

pgain_current

 [31:14] Reserved - -
[13:0] P gain coefficient for current control loop * 1000 20 RW

0x4C

igain_current

 [31:14] Reserved - -
[13:0] I gain coefficient for current control loop * V 25 RW
Table 34.  FFT IP RegistersWrite reserved bits as zero and read as zero. R/W1C bits are read, write a 1 to clear the bit
Address Name Bits Description Reset Value Access
0x00 busy [31:1] Reserved - -
[0] FFT data input Not ready, busy flag. 0x0 R
0x04 start [31:1] Reserved - -
[0] Start command. When write a new input data for FFT toggle this bit 0 to 1. 0x0 RW
0x40 SIZE_CFG [31:4] Reserved - -
[3:0] Power of 2 of FFT size. When set n, FFT size is 2^n. RW
0x80 D_input [31:16] Reserved - -
[15:0] Input data for FFT RW
Level Two Title