AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

ID 683072
Date 4/22/2021
Public
Document Table of Contents

2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices

  • Multiple FOC loop implementations:
    • Fixed- and floating-point implementation with Nios II processors targeting Intel® MAX® 10 FPGA devices
    • Fixed- and floating-point accelerator implementations designed using Simulink* model-based design flow with DSP Builder for Intel FPGAs
    • Selectable 16 kHz or 32 kHz control loop update
  • Integration in a single Intel® MAX® 10 FPGA of single and multiaxis motor control IP including:
    • High performance PWM IP at 300 MHz for two-level IGBT or MOSFET power stages
    • Sigma delta ADC interfaces for motor current feedback and DC link voltage measurement
    • Direct connection to MAX 10 integrated ADC
    • Multiple position feedback interfaces (default quadrature encoder)
  • Bidirectional DC-DC converter for Tandem Motion-Power 48 V Board
    • 9 to 16 V input
    • 12 to 48 V output
    • System Console toolkit GUI for motor feedback information and control of motors
  • Optional support for rechargeable battery power and BMS development with state-of-charge (SOC) estimation using an adaptive Dual Extended Kalman Filter (DEKF) algorithm

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