AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

ID 683072
Date 7/26/2023
Document Table of Contents

7.11. FOC Subsystem

The Drive-on-Chip Design uses DSP Builder for Intel FPGAs to generate the HDL code for floating-point and fixed-point implementations of the field-oriented control (FOC) algorithm. The processor uses this DSP Builder-generated FOC IP as a coprocessor and moves the data between the FOC IP and the peripherals.
Note: Alternatively, the design includes software implementations of the FOC algorithm with the same FOC functionality. You can select which implementation to run using the Debug GUI. In the floating-point FOC DSP builder implementation, the design performs the SVM function in software. In the fixed point FOC DSP builder implementation, the SVM function is in the IP.

FOC controls a motor's sinusoidal 3-phase currents in real time to create a smoothly rotating magnetic flux pattern, where the frequency of rotation corresponds to the frequency of the sine waves. FOC controls the current vector to keep:

  • The torque-producing quadrature current, Iq, at 90 degrees to the rotor magnet flux axis
  • The direct current component, Id, (commanded to be zero) inline with the rotor magnet flux.

The FOC algorithm:

  1. Converts the 3-phase feedback current inputs and the rotor position from the encoder into quadrature and direct current components using Clarke and Park transforms.
  2. Uses these current components as the inputs to two proportional and integral (PI) controllers running in parallel to adjust the direct current to zero and the quadrature current to the desired torque.
  3. Converts the direct and quadrature voltage outputs from the PI controllers back to 3-phase voltages with inverse Clarke and Park transforms.

The FOC algorithm includes:

  • Forward and reverse Clarke and Park transforms
  • Direct and quadrature current
  • Proportional integral (PI) control loops
  • Sine and cosine
  • Saturate functions