AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

ID 683072
Date 4/22/2021
Public
Document Table of Contents

7.4.1. Drive System Monitor States for the Drive-On-Chip Design Example

Table 10.  Drive System Monitor States
State Name System State
0 Idle Reset state, moves immediately to preinit
1 Precharge PWM counter running, low side outputs enabled, voltage errors monitored
2 Prerun PWM counter running, low side outputs enabled, voltage and current errors monitored
3 Run PWM counter running, low and high side outputs enabled, voltage and current errors monitored
4 Error Error state, PWM counter running, outputs disabled
5 init PWM counter running, outputs disabled, voltage errors monitored
6 preinit PWM counter running, outputs disabled

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