AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

ID 683072
Date 7/26/2023
Document Table of Contents

7.11.7. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs

You can manually regenerate the VHDL for any of the DSP Builder models. The models are in <project>/non_qpds_ip/dsp_builder_models
  1. Start DSP Builder for Intel FPGAs.
  2. Change the directory to the ip\dspba .
  3. If you want a different numeric precision, edit the setup_<Simulink Model>.m file corresponding to the model before opening it.
  4. Load the model (slx extension). Check the status of the orange DSP Builder folding block. If the model includes it, folding is enabled. If it is removed or commented out, the model does not use folding.
  5. On the Simulation menu, click Start.

    DSP Builder for Intel FPGAs generates the VHDL files in ip\dspba\rtl (for Cyclone V devices) or ip\dspba\rtlmax10 (for MAX 10 devices).