AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

ID 683072
Date 7/26/2023
Document Table of Contents

11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices

Version Changes
2023.07.26 Updated download link in Downloading and Installing the Drive-On-Chip Design Example
2023.07.17 Corrected list of demonstrations in System Console GUI Lower Pane for the Drive-On-Chip Design Example
2023.07.07 Corrected design version typos in Debugging and Monitoring the Drive-On-Chip Design Example with System Console and Programming the Nios II Software to the Device for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
  • Changed configuration macro SD_ADC_FILTER range from 20 to 50 us
  • Added High-speed FOC with Position Sensor Feedback to Motor Control Modes
  • Changed:
    • FOC Subsystem
    • DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs
    • Signals
    • Registers
  • Changed ADC scaling value.
  • Changed signal scaling architecture figure.
  • Deleted Scaling for DC-DC Converter Feedback Samples tables
  • Changed DC Link Monitor
  • Updated DC-DC Converter
  • Added DC-DC Control Simulink Models
  • Added Sigma-Delta ADC Interface for DC-DC Converter
  • Updated DC-DC Converter Control and Status Registers
2021.02.15 Changed PWM frequency from 333 MHz to 300 MHz
  • Removed FalconEye 2 HSMC board.
  • Renamed to design example.
  • Added Achieving Timing Closure on Motor Control Designs
  • removed EnDat Encoder Interface and BiSS Encoder Interface
  • Added support for estimating battery state of charge (SOC).
  • Changed name from Drive-on-Chip Reference Design v16.0 to Drive-on-Chip Reference Design for MAX 10 Devices.
  • Rebranded as Intel.
2017.01.10 Initial release.