AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

ID 683072
Date 4/22/2021
Public
Document Table of Contents

7.13. Signals

The signals connect various blocks in the Drive-On-Chip Design Example for Intel® MAX® 10 devices.
Table 18.  Six-Channel PWM Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input PWM and system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
Conduit Signals
pwm_enable Input PWM enable from drive system monitor
en_upper Input Upper switch enable from drive system monitor
en_lower Input Lower switch enable from drive system monitor
u_h Output Motor phase phase U upper gate drive
u_l Output Motor phase phase U lower gate drive
v_h Output Motor phase phase V upper gate drive
v_l Output Motor phase phase V lower gate drive
w_h Output Motor phase phase W upper gate drive
w_l Output Motor phase phase W lower gate drive
sync_in Input Synchronization signal for multiple PWM modules
sync_out Output Synchronization signal for multiple PWM modules
start_adc Output ADC start conversion signal
Table 19.  DC Link Monitor Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
clk_adc Input ADC clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
avs_irq Output Avalon interrupt
Conduit Signals
sync_dat Input Sigma-delta ADC bit stream
dc_link_enable Input Enable
overvoltage Input Overvoltage status
undervoltage Output Undervoltage status
chopper Output Chopper circuit gate drive
Table 20.  Drive System Monitor Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
Conduit Signals
overcurrent Input Overcurrent status
overvoltage Input Overvoltage status
undervoltage Input Undervoltage status
chopper Input Chopper status
dc_link_clk_err Input Clock monitor status
igbt_err Input IGBT error status
error_out Output Error output
overcurrent_latch Output Latched overcurrent status
overvoltage_latch Output Latched overvoltage status
undervoltage_latch Output Latched undervoltage status
dc_link_clk_err_latch Output Latched clock monitor status
igbt_err_latch Output Latched IGBT error status
chopper_latch Output Latched chopper status
pwm_control[2:0] Output PWM control
Table 21.  Quadrature Encoder Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
Conduit Signals
strobe Input Capture strobe
QEP_A Input Quadrature phase A
QEP_B Input Quadrature phase B
QEP_I Input Quadrature index
Table 22.  Sigma-Delta ADC Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
clk_adc Input ADC clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
avs_irq Output Interrupt request
Conduit Signals
start Input Start conversion signal
sync_dat_u Input Phase U sigma-delta bitstream
sync_dat_v Input Phase V sigma-delta bitstream
sync_dat_w Input Phase W sigma-delta bitstream
overcurrent Output Overcurrent status
Table 23.  MAX 10 ADC Threshold Sink Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
Avalon-ST Sink Interface Signals
st_1_valid Input ADC 1 threshold valid
st_1_channel[4:0] Input ADC 1 threshold channel index
st_1_data Input ADC 1 threshold data
st_2_valid Input ADC 2 threshold valid
st_2_channel[4:0] Input ADC 2 threshold channel index
st_2_data Input ADC 2 threshold data
Conduit Signals
under[15:0] Output Under threshold errors
over[15:0] Output Over threshold errors
Table 24.  DC-DC Converter Interface Signals
Signal Name Direction Description
Avalon memory-mapped interface signals
avs_clk Input 10MHz clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[4:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM read data bus
avs_readdata[31:0] Output Avalon-MM write data bus
Conduit Signals
enable_in Input Enable input
bidir_en_n Input Bidirectional conversion enable
fault Input Fault input. If the design asserts the fault input, it clears the enable bit of the control register, and turns off the DC-DC converter. The design keeps the enable bit clear, and does not set again, until the fault input is negated.
pwm_sync_n Input Synchronization signal
gate_a_h Output Phase 0 upper transistor gate drive
gate_a_l Output Phase 0 lower transistor gate drive
gate_b_h Output Phase 1 upper transistor gate drive
gate_b_l Output Phase 1 lower transistor gate drive
dc_dc_on Output DC-DC status
overvoltage Output Overvoltage error
overcurrent Output Overcurrent error
timeout_latch Output Sample timeout
sync_dat_i_pase_a Input Phase 0 current feedback sigma-delta bitstream
sync_dat_i_pase_b Input Phase 1 current feedback sigma-delta bitstream
sync_dat_v_out Input Voltage feedback sigma-delta bitstream
clk_adc Input ADC clock input

Did you find the information on this page useful?

Characters remaining:

Feedback Message