AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

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ID 683072
Date 7/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices 3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 5. About the Scaling of Feedback Signals 6. Motor Control Software 7. Functional Description of the Drive-on-Chip Design Example 8. Achieving Timing Closure on a Motor Control Design 9. Design Security Recommendations 10. Reference Documents for the Drive-on-Chip Design Example 11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.1. Software Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up the Motor Control Board with your Development Board for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.5. Importing the Drive-On-Chip Design Example Software Project 3.6. Configuring the FPGA Hardware for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.7. Programming the Nios II Software to the Device for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.8. Applying Power to the Power Board 3.9. Debugging and Monitoring the Drive-On-Chip Design Example with System Console 3.10. System Console GUI Upper Pane for the Drive-On-Chip Design Example 3.11. System Console GUI Lower Pane for the Drive-On-Chip Design Example 3.12. Controlling the DC-DC Converter 3.13. Tuning the PI Controller Gains 3.14. Controlling the Speed and Position Demonstrations 3.15. Monitoring Performance
3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.2.1. Preparing the Rechargeable Battery
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
4.1. Changing the Intel® MAX® 10 ADC Thresholds or Conversion Sequence 4.2. Generating the Qsys System 4.3. Compiling the Hardware in the Intel Quartus Prime Software 4.4. Generating and Building the Nios II BSP for the Drive-On-Chip Design Example 4.5. Software Application Configuration Files 4.6. Compiling the Software Application for the Drive-On-Chip Design Example 4.7. Programming the Design into Flash Memory
4.5. Software Application Configuration Files x
4.5.1. Defining a New Motor or Encoder Type
5. About the Scaling of Feedback Signals x
5.1. Signal Sensing in Sigma-Delta and MAX 10 Integrated ADCs 5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 5.3. Scale Factors for the Drive-on-Chip Design Example in the System Console Toolkit
6. Motor Control Software x
6.1. Viewing Motor Control Software Help Files
7. Functional Description of the Drive-on-Chip Design Example x
7.1. Processor Subsystem 7.2. Six-channel PWM Interface 7.3. DC Link Monitor 7.4. Drive System Monitor 7.5. Quadrature Encoder Interface 7.6. Sigma-Delta ADC Interface for Drive Axes 7.7. Intel® MAX® 10 ADCs 7.8. ADC Threshold Sink 7.9. DC-DC Converter 7.10. Motor Control Modes 7.11. FOC Subsystem 7.12. DEKF Technique 7.13. Signals 7.14. Registers
7.4. Drive System Monitor x
7.4.1. Drive System Monitor States for the Drive-on-Chip Design Example
7.6. Sigma-Delta ADC Interface for Drive Axes x
7.6.1. Offset Adjustment for Sigma-Delta ADC Interface
7.9. DC-DC Converter x
7.9.1. DC-DC Control Simulink Models 7.9.2. Sigma-Delta ADC Interface for DC-DC Converter
7.9.1. DC-DC Control Simulink Models x
7.9.1.1. DC-DC Control Block 7.9.1.2. Generating VHDL for the DSP Builder for Intel FPGAs Models for the DC-DC Converter
7.9.1.1. DC-DC Control Block x
7.9.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format
7.11. FOC Subsystem x
7.11.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs 7.11.2. Avalon Memory-Mapped Interface 7.11.3. About DSP Builder for Intel FPGAs 7.11.4. DSP Builder for Intel FPGAs Folding 7.11.5. DSP Builder for Intel FPGAs Model Resource Usage 7.11.6. DSP Builder for Intel FPGAs Design Guidelines 7.11.7. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
8. Achieving Timing Closure on a Motor Control Design x
8.1. Optimizing Motor Control Designs
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example
8. Achieving Timing Closure on a Motor Control Design
9. Design Security Recommendations
10. Reference Documents for the Drive-on-Chip Design Example
11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices

7.13. Signals

The signals connect various blocks in the Drive-On-Chip Design Example.
Table 20.  Six-Channel PWM Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input PWM and system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
Conduit Signals
pwm_control [2:0] Input
  • en_upper: Upper switch enable from drive system monitor.
  • en_lower: Lower switch enable from drive system monitor.
  • pwm_enable: PWM enable from drive system monitor
vu_pwm Input PWM value for phase U voltage
vv_pwm Input PWM value for phase V voltage
vw_pwm Input PWM value for phase W voltage
u_h Output Motor phase U upper gate drive
u_l Output Motor phase U lower gate drive
v_h Output Motor phase V upper gate drive
v_l Output Motor phase V lower gate drive
w_h Output Motor phase W upper gate drive
w_l Output Motor phase W lower gate drive
sync_in Input Synchronization signal for multiple PWM modules
sync_out Output Synchronization signal for multiple PWM modules
start_adc Output ADC start conversion signal
Table 21.  DC Link Monitor Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
clk_adc Input ADC clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
avs_irq Output Avalon interrupt
Conduit Signals
sync_dat Input Sigma-delta ADC bit stream
dc_link_enable Input Enable
overvoltage Input Overvoltage status
undervoltage Output Undervoltage status
chopper Output Chopper circuit gate drive
Table 22.  Drive System Monitor Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
Conduit Signals
overcurrent Input Overcurrent status
overvoltage Input Overvoltage status
undervoltage Input Undervoltage status
chopper Input Chopper status
dc_link_clk_err Input Clock monitor status
igbt_err Input IGBT error status
error_out Output Error output
overcurrent_latch Output Latched overcurrent status
overvoltage_latch Output Latched overvoltage status
undervoltage_latch Output Latched undervoltage status
dc_link_clk_err_latch Output Latched clock monitor status
igbt_err_latch Output Latched IGBT error status
chopper_latch Output Latched chopper status
pwm_control[2:0] Output PWM control
Table 23.  Quadrature Encoder Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
Conduit Signals
strobe Input Capture strobe
QEP_A Input Quadrature phase A
QEP_B Input Quadrature phase B
QEP_I Input Quadrature index
Table 24.  Sigma-Delta ADC Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
clk_adc Input ADC clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
avs_irq Output Interrupt request
Conduit Signals
start Input Start conversion signal
sync_dat_u Input Phase U sigma-delta bitstream
sync_dat_v Input Phase V sigma-delta bitstream
sync_dat_w Input Phase W sigma-delta bitstream
Iu_reg [15:0] Output Registers to hold synchronized phase U current
Iw_reg[15:0] Output Registers to hold synchronized phase W current
Iu_reg_156[15:0] Output Registers to hold free running phase U current, not in use.
Iw_reg_156[15:0] Output Registers to hold free running phase W current, not in use.
overcurrent Output Overcurrent status
Table 25.  MAX 10 ADC Threshold Sink Interface Signals
Signal Name Direction Description
Avalon-MM Interface Signals
clk Input FPGA system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[3:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM write data bus
avs_readdata[31:0] Output Avalon-MM read data bus
Avalon-ST Sink Interface Signals
st_1_valid Input ADC 1 threshold valid
st_1_channel[4:0] Input ADC 1 threshold channel index
st_1_data Input ADC 1 threshold data
st_2_valid Input ADC 2 threshold valid
st_2_channel[4:0] Input ADC 2 threshold channel index
st_2_data Input ADC 2 threshold data
Conduit Signals
under[15:0] Output Under threshold errors
over[15:0] Output Over threshold errors
Table 26.  DC-DC Converter Interface Signals
Signal Name Direction Description
Avalon memory-mapped interface signals
avs_clk Input 10MHz clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon-MM read strobe, active low
avs_write_n Input Avalon-MM write strobe, active low
avs_address[4:0] Input Avalon-MM address bus
avs_writedata[31:0] Input Avalon-MM read data bus
avs_readdata[31:0] Output Avalon-MM write data bus
Conduit Signals
enable_in Input Enable input
bidir_en_n Input Bidirectional conversion enable
fault Input Fault input. If the design asserts the fault input, it clears the enable bit of the control register, and turns off the DC-DC converter. The design keeps the enable bit clear, and does not set again, until the fault input is negated.
pwm_sync_n Input Synchronization signal
gate_a_h Output Phase 0 upper transistor gate drive
gate_a_l Output Phase 0 lower transistor gate drive
gate_b_h Output Phase 1 upper transistor gate drive
gate_b_l Output Phase 1 lower transistor gate drive
dc_dc_on Output DC-DC status
overvoltage Output Overvoltage error
overcurrent Output Overcurrent error
timeout_latch Output Sample timeout
sync_dat_i_pase_a Input Phase 0 current feedback sigma-delta bitstream
sync_dat_i_pase_b Input Phase 1 current feedback sigma-delta bitstream
sync_dat_v_out Input Voltage feedback sigma-delta bitstream
clk_adc Input ADC clock input
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