AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

ID 683072
Date 7/26/2023
Document Table of Contents

7.11.3. About DSP Builder for Intel FPGAs

DSP Builder for Intel FPGAs supports bit-accurate simulation and VHDL generation of the full range of fixed-point and floating-point data types available in Simulink*. Floating-point data types give a high dynamic range, avoid arithmetic overflows, and avoid the manual floating- to fixed-point conversion and scaling steps necessary in algorithm development. You can optimize the data types to adjust hardware usage and calculation latency, and run Simulink* simulations to confirm adequate performance.

After you develop the algorithm in Simulink*, DSP Builder can automatically generate pipelined HDL that it targets and optimizes to the chosen FPGA device. You can use this VHDL in a HDL simulator such as ModelSim* to verify the generated logic versus Simulink* and in the Quartus Prime software to compile the hardware. DSP Builder for Intel FPGAs gives instant feedback of the VHDL's logic utilization and algorithm latency in automatically generated Simulink* reports.