Programming Guide

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Types of SYCL* FPGA Compilation

SYCL supports accelerators in general. The Intel® oneAPI DPC++/C++ Compiler implements additional FPGA-specific support to assist FPGA code development. This article highlights FPGA development using the compiler and related tools for SYCL code development targeting FPGAs.
The following table summarizes the types of FPGA compilation:
Types of FPGA Compilation
Device Image Type
Time to Compile
Description
FPGA Emulator
Seconds
Compiles the FPGA device code to the CPU. Use the Intel® FPGA Emulation Platform for OpenCL™ software to verify your SYCL code’s functional correctness.
FPGA Simulator
Minutes
Compiles the FPGA device code to the CPU. Use the Questa*-Intel® FPGA Edition simulator to debug your code.
Optimization Report
Minutes
Partially compiles the FPGA device code for hardware. The compiler generates an optimization report that describes the structures generated on the FPGA, identifies performance bottlenecks, and estimates resource utilization.
FPGA Hardware Image
Hours
Generates the real FPGA bitstream to execute on the target FPGA platform.
A typical FPGA development workflow is to iterate in each of these stages, refining the code using the feedback provided by each stage. Intel® recommends relying on emulation and the FPGA optimization report whenever possible.
To compile for FPGA emulation or generate the FPGA optimization report, you require only the Intel® oneAPI DPC++/C++ Compiler that is part of the Intel® oneAPI Base Toolkit. However, an FPGA hardware compile requires installing the Intel® Quartus® Prime Pro Edition software and the BSP separately. For more information, refer to the Intel® oneAPI Toolkits Installation Guide and Intel® FPGA development flow webpage.

FPGA Emulator

The FPGA emulator (Intel® FPGA Emulation Platform for OpenCL™ software) is the fastest method to verify the correctness of your code. It executes the SYCL device code on the CPU. The emulator is similar to the SYCL host device, but unlike the host device, the FPGA emulator device supports FPGA extensions such as FPGA pipes and
fpga_reg
. For more information, refer to Pipes Extension and Kernel Variables topics in the
FPGA Optimization Guide for Intel® oneAPI Toolkits
.
The following are some important caveats to remember when using the FPGA emulator:
  • Performance is not representative
    .
    Never draw inferences about FPGA performance from the FPGA emulator. The FPGA emulator’s timing behavior is not correlated to that of the physical FPGA hardware. For example, an optimization that yields a 100x performance improvement on the FPGA may not impact the emulator performance. The emulator might show an unrelated increase or decrease.
  • Undefined behavior may differ
    .
    If your code produces different results when compiled for the FPGA emulator versus FPGA hardware, your code most likely exercises undefined behavior. By definition, undefined behavior is not specified by the language specification and might manifest differently on different targets.
For detailed information about emulation, refer to Emulate Your Design.

FPGA Simulator

The simulation flow allows you to use the Questa*-Intel® FPGA Edition simulator software to simulate the exact behavior of the synthesized kernel. Like emulation, you can run simulation on a system that does not have a target FPGA board installed. The simulator models a kernel much more accurately than the emulator, but it is much slower than the emulator.
The simulation flow is cycle-accurate and bit-accurate. It exactly models the behavior of a kernel’s datapath and the results of operations on floating-point data types. However, simulation cannot accurately model variable-latency memories or other external interfaces. Intel® recommends that you simulate your design with a small input dataset because simulation is much slower than running on FPGA hardware or emulator.
You can use the simulation flow in conjunction with profiling to collect additional information about your design. For more information about profiling, refer to Intel® FPGA Dynamic Profiler for DPC++ in the
FPGA Optimization Guide for Intel® oneAPI Toolkits
.
You cannot debug kernel code compiled for simulation using the GNU Project Debugger (GDB)*, Microsoft Visual Studio*, or any standard software debugger.
For more information about the simulation flow, refer to Evaluate Your Kernel Through Simulation.

FPGA Optimization Report

A full FPGA compilation occurs in the following stages, and optimization reports are generated after both stages:
FPGA Optimization Report
Stages
Description
Optimization Report Information
FPGA early image
(Compilation takes minutes to complete)
The SYCL device code is optimized and converted into an FPGA design specified in the Verilog Register-Transfer Level (RTL) (a low-level, native entry language for FPGAs). The intermediate compilation result is the FPGA early device image that is not an executable.
The optimization report generated at this stage is sometimes referred to as the
static report
.
Contains important information about how the compiler has transformed your SYCL device code into an FPGA design. The report includes the following information:
  • Visualizations of structures generated on the FPGA.
  • Performance and expected performance bottleneck.
  • Estimated resource utilization.
For information about the FPGA optimization report, refer to the FPGA Optimization Guide for Intel® oneAPI Toolkits.
FPGA hardware image
(Compilation takes hours to complete)
The Verilog RTL specifying the design’s circuit topology is mapped onto the FPGA’s primitive hardware resources by the Intel® Quartus® Prime pro Edition Software. The result is an FPGA hardware binary (also referred to as a bitstream).
Contains precise information about resource utilization and f
MAX
numbers. For detailed information about how to analyze reports, refer to Analyze your Design section in the
FPGA Optimization Guide for Intel® oneAPI Toolkits
.
For information about the FPGA hardware image, refer to the FPGA Optimization Guide for Intel® oneAPI Toolkits.

FPGA Hardware

This is a full compilation stage through to the FPGA hardware image. You can target the Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA, the Intel® FPGA PAC D5005 (previously known as
Intel® PAC with Intel® Stratix® 10 SX FPGA
), or a custom board.
For more information about using Intel® PAC or custom boards, refer to the FPGA BSPs and Boards section.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.