Intel® FPGA Add-on for oneAPI Base Toolkit
Use Reconfigurable Hardware to Accelerate Data-Centric Workloads
Accelerate Your Data-Centric Workloads with FPGAs
FPGA is an acronym for field programmable gate array. An FPGA is an integrated circuit whose electrical functionality can be changed, even after the device is shipped to customers in the field. FPGAs offer incredible flexibility and cost efficiency with circuitry that can be reprogrammed for different functionalities. The Intel® FPGA Add-on for oneAPI Base Toolkit is a specialized component for programming such reconfigurable FPGA devices.
Benefits
- Accelerate your FPGA workloads effortlessly.
- Reduce FPGA development time by weeks.
- Implement complex hardware designs using SYCL*, a modern C++ language extension.
- Refine your designs with quick iterative development workflows.
- Analyze design performance graphically with Intel® VTune™ Profiler.
- Generate register-transfer level (RTL) bitstream with the included license-free Intel® Quartus® Prime Pro Edition Software version 22.2 for Linux*.
FPGA Development & Deployment
Develop and optimize an FPGA workload with the Intel® oneAPI Base Toolkit. The oneAPI output is a performance-accurate FPGA hardware model of the algorithm.
Accelerate your workload by using the Intel Quartus Prime Pro Edition Software to link the oneAPI FPGA hardware model to the supported FPGA platform.
Choose the Right FPGA and Software
Intel Quartus Prime Pro Edition Software is an add-on to the Intel oneAPI Base Toolkit and compiles the FPGA hardware models generated by oneAPI with those in the FPGA platform to program the FPGA. Intel Quartus Prime Pro Edition Software is not required to develop accurate FPGA hardware models using oneAPI but is required to compile and run on the FPGA platform.
Instructions
To accelerate your algorithm on an FPGA platform, choose an FPGA platform and corresponding software.
- Locate the FPGA platform that you are targeting for your application.
- To get and install the FPGA platform and its board support package (BSP), go to the vendor website.
- Download and install the required version of Intel Quartus Prime Pro Edition Software for Linux.
| FPGA Platform | BSP | Intel® Quartus® Prime Pro Edition Software for Linux |
|---|---|---|
BittWare* |
Purchase Platform | Version 21.4 |
BittWare |
Purchase Platform | Version 20.4 |
Hitek Systems* |
Purchase Platform | Version 22.2 |
Intel Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA |
Platform Deprecated: |
Version 19.2 |
Intel |
Platform Deprecated: |
Version 19.2 |
Terasic |
Version 21.2 |
FPGA Options
Evaluate oneAPI acceleration solutions on Intel FPGAs to move, process, and store data faster and more efficiently. You can access Intel’s latest software and hardware offerings for free on the Intel® Developer Cloud.
Code Samples
Learn how to compile Data Parallel C++ (DPC++) applications for FPGAs (spatial compute architectures) through a simple vector addition example. Recommended for developers new to DPC++ for FPGAs.
See how to separate the compilation of a program's host code and device code to save development time. The FPGA Compile Flow tutorial is a recommended prerequisite.
Learn how to use the [[intel::kernel_args_restrict]] kernel attribute, which allows you to guarantee that kernel arguments do not alias, thereby enabling more aggressive compiler optimizations and often kernel performance improvements on FPGA.
This tutorial demonstrates the loop unrolling mechanism that is used to increase program parallelism by duplicating the compute logic within a loop.
See how a kernel in a DPC++ FPGA program transfers data to or from another kernel using the pipe abstraction. This allows concurrent execution of kernels that need to exchange data.
Learn how to use on-chip memory attributes to control memory structures in your DPC++ program. These samples are a set of DPC++ extensions for FPGAs that enable you to override the compiler's internal heuristics and control the kernel's memory architecture, maximizing the overall throughput.
This sample demonstrates an alternative coding style, SYCL* Unified Shared Memory (USM) device allocations, in which data movement between host and device is controlled explicitly by the code author.
This demonstration shows how to parallelize host-side processing and buffer transfers between host and device with running kernels, which can improve overall application performance.
Reference Designs
Adaptive Noise Reduction (ANR)
This reference design depicts a parameterizable image processing pipeline that implements an ANR algorithm using a bilateral filter on Intel FPGAs.
Minimum Variance Distortionless Response (MVDR) Beamforming
A high-performance streaming I/O (such as host and ethernet) design that implements an MVDR-beamforming algorithm on Intel FPGAs.
This example shows database query acceleration workloads when offloading from a CPU to an FPGA for a data-warehouse schema derived from TPC-H.
This algorithm includes accelerated tasks that implement Limpel-Ziv 77 (LZ77), Static Huffman, and CRC algorithms.
This example shows a decomposition of matrices of complex numbers, a common operation employed in linear algebra.
Cox-Ross-Rubinstein (CRR) Binomial Tree Model for Option Pricing
This model is used in the finance field for American exercise options with five Greeks (delta, gamma, theta, vega, and rho).
Documentation
Guides & Specifications
Get Help
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For additional help, see our general oneAPI Support.
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Product and Performance Information
The FPGA Add-On is intended to be used in conjunction with the Intel oneAPI DPC++ Compiler, which is part of the Intel® oneAPI Base Toolkit. Installation of both the base toolkit and this add-on are required to work through the compile stage of the FPGA design flow.
Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.