Intel® FPGA Add-on for oneAPI Base Toolkit
Use Reconfigurable Hardware to Accelerate Data-Centric Workloads
Accelerate Your Data-Centric Workloads with FPGAs
FPGA is an acronym for field programmable gate array. An FPGA is an integrated circuit whose electrical functionality can be changed, even after the device is shipped to customers in the field. FPGAs offer incredible flexibility and cost efficiency with circuitry that can be reprogrammed for different functionalities. The Intel® FPGA Add-on for oneAPI Base Toolkit is a specialized component for programming such reconfigurable FPGA devices.
Benefits
- Accelerate your FPGA workloads effortlessly.
- Reduce FPGA development time by weeks.
- Implement complex hardware designs using SYCL*, a modern C++ language extension.
- Refine your designs with quick iterative development workflows.
- Analyze design performance graphically with Intel® VTune™ Profiler.
- Generate register-transfer level (RTL) bitstream with the included license-free Intel® Quartus® Prime Pro Edition software.
Development Flow
Evaluate oneAPI acceleration solutions on Intel FPGAs to move, process, and store data faster and more efficiently. You can access Intel’s latest software and hardware offerings for free on the Intel® DevCloud.
Intel® Arria® 10 FPGAs
These FPGAs deliver more than speed-grade faster core performance and up to 20% fMAX advantage compared to the competition by using publicly available OpenCores* designs. Intel® Arria® 10 FPGAs provide up to 40% lower power than previous generation FPGAs. They feature the industry’s only hard floating-point digital signal processing (DSP) blocks with speeds up to 1.5 tera floating-point operations per second (TFLOPS).
Explore the Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA
Intel® Stratix® 10 FPGAs
Take advantage of innovative advances in performance, power efficiency, density, and system integration. Intel® Stratix® 10 devices deliver up to 2x performance gains over previous generation high-performance FPGAs. They feature the revolutionary Intel® Hyperflex™ FPGA Architecture, Intel's patented Embedded Multi-die Interconnect Bridge (EMIB) technology, and Advanced Interface Bus (AIB).
Explore the Intel® FPGA Programmable Acceleration Card D5005
Intel® Agilex™ FPGA
These FPGA devices use heterogeneous 3D system-in-package (SiP) technology to integrate Intel’s first FPGA fabric built on 10 nm SuperFin Technology. This advanced process technology and 2nd generation Intel® Hyperflex™ FPGA Architecture enables these FPGAs to deliver up to 2x better fabric performance per watt2 when compared to third-party 7 nm FPGA portfolio.
Code Samples
Learn how to compile Data Parallel C++ (DPC++) applications for FPGAs (spatial compute architectures) through a simple vector addition example. Recommended for developers new to DPC++ for FPGAs.
See how to separate the compilation of a program's host code and device code to save development time. The FPGA Compile Flow tutorial is a recommended prerequisite.
Learn how to use the [[intel::kernel_args_restrict]] kernel attribute, which allows you to guarantee that kernel arguments do not alias, thereby enabling more aggressive compiler optimizations and often kernel performance improvements on FPGA.
This tutorial demonstrates the loop unrolling mechanism that is used to increase program parallelism by duplicating the compute logic within a loop.
See how a kernel in a DPC++ FPGA program transfers data to or from another kernel using the pipe abstraction. This allows concurrent execution of kernels that need to exchange data.
Learn how to use on-chip memory attributes to control memory structures in your DPC++ program. These samples are a set of DPC++ extensions for FPGAs that enable you to override the compiler's internal heuristics and control the kernel's memory architecture, maximizing the overall throughput.
This sample demonstrates an alternative coding style, SYCL* Unified Shared Memory (USM) device allocations, in which data movement between host and device is controlled explicitly by the code author.
This demonstration shows how to parallelize host-side processing and buffer transfers between host and device with running kernels, which can improve overall application performance.
Reference Designs
Adaptive Noise Reduction (ANR)
This reference design depicts a parameterizable image processing pipeline that implements an ANR algorithm using a bilateral filter on Intel FPGAs.
Minimum Variance Distortionless Response (MVDR) Beamforming
A high-performance streaming I/O (such as host and ethernet) design that implements an MVDR-beamforming algorithm on Intel FPGAs.
This example shows database query acceleration workloads when offloading from a CPU to an FPGA for a data-warehouse schema derived from TPC-H.
This algorithm includes accelerated tasks that implement Limpel-Ziv 77 (LZ77), Static Huffman, and CRC algorithms.
This example shows a decomposition of matrices of complex numbers, a common operation employed in linear algebra.
Cox-Ross-Rubinstein (CRR) Binomial Tree Model for Option Pricing
This model is used in the finance field for American exercise options with five Greeks (delta, gamma, theta, vega, and rho).
Documentation
Guides & Specifications
Get Help
- Intel oneAPI Base Toolkit
- Intel oneAPI DPC++/C++ Compiler
- Intel VTune Profiler
- FPGA and High-Level Design from Intel
For additional help, see our general oneAPI Support.
Product and Performance Information
The FPGA Add-On is intended to be used in conjunction with the Intel oneAPI DPC++ Compiler, which is part of the Intel® oneAPI Base Toolkit. Installation of both the base toolkit and this add-on are required to work through the compile stage of the FPGA design flow.
Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.