Download the Base Kit

The Base Kit is foundational to all FPGA workflows.

  • Develop and optimize an FPGA workload with the Base Kit.
  • Review a performance-accurate FPGA hardware model of the algorithm using detailed reports and graphical analysis views.


Download the Intel FPGA Add-on for oneAPI Base Toolkit

Link your new or existing FPGA hardware model with an FPGA platform model to create an executable FPGA bitstream through the Intel Quartus Prime Pro Edition Software.

  • Acceleration flow: Choose an FPGA platform.
  • Develop hardware IP: Start with the oneAPI IP Authoring flow

Get Started with oneAPI IP Authoring


Start Developing

Browse the examples and reference designs to help you design and implement high-performance hardware. Run your own workloads with the help of tutorials and training.

Try out an FPGA and access Intel’s latest software and hardware offerings for free on the Intel® Developer Cloud

Learn More about Intel Developer Cloud


Intuitive Code Development Environment

Validate and debug your algorithm. Optimize application and system performance, and the system configuration.

  • Validate algorithms with SYCL in minutes rather than days with RTL simulation.
  • Debug and analyze using Intel VTune Profiler and Intel® Distribution for GDB*.
  • Take advantage of a project-based graphical environment.

Intel VTune Profiler

Intel Distribution for GDB


High-Performance Hardware

Review results through reports and gain optimization insights with an advanced graphical analysis environment.

  • Cycle-accurate RTL models generated from SYCL within minutes.
  • Direct control over interface protocols.
  • Automatic performance goals.
  • Detailed graphical analysis views on code elaboration, cycle scheduling, and sharing.


Automatic RTL Verification

Confirm the accuracy of the generated hardware with built-in hardware verification.

  • Confirm the RTL hardware model matches the SYCL source with push-button verification.
  • Generate RTL testbenches automatically.
  • Simulate RTL automatically to verify that RTL matches the SYCL results.

Get Started with FPGA Verification