A newer version of this document is available. Customers should click here to go to the newest version.
Viewing Simulation Waveforms
By default, the Intel oneAPI DPC++/C++ Compiler instructs the simulator not to log any signals because logging signals slows the simulation, and the waveform files are enormous. However, you can configure the compiler to save these waveforms for debugging purposes.
To enable signal logging in the simulator, invoke the icpx command with the -Xsghdl option, as follows:
icpx -fsycl -fintelfpga -Xssimulation -Xsghdl[=<depth>] <input files> -o <project_name>
Specify the <depth> attribute to indicate the number of hierarchy levels logged. A depth value of 1 logs only the top-level signals. A depth of 1 is used as the default if you do not specify the <depth> attribute.
After running the simulation, you can view the generated waveform files by invoking the appropriate script as follows:
Did you find the information on this page useful?