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Why is FPGA Compilation Different? Types of SYCL* FPGA Compilation FPGA Compilation Flags Emulate and Debug Your Design Evaluate Your Kernel Through Simulation Device Selectors for FPGA FPGA IP Authoring Flow Fast Recompile for FPGA Generate Multiple FPGA Images (Linux only) FPGA BSPs and Boards Targeting Multiple Homogeneous FPGA Devices Targeting Multiple Platforms FPGA-CPU Interaction FPGA Performance Optimization Use of RTL Libraries for FPGA Use SYCL Shared Library With Third-Party Applications FPGA Workflows in IDEs
Intel oneAPI DPC++ Library (oneDPL) Intel oneAPI Math Kernel Library (oneMKL) Intel oneAPI Threading Building Blocks (oneTBB) Intel oneAPI Data Analytics Library (oneDAL) Intel oneAPI Collective Communications Library (oneCCL) Intel oneAPI Deep Neural Network Library (oneDNN) Intel oneAPI Video Processing Library (oneVPL) Other Libraries
The host pipe implementation is a prototype implementation that relies on prototype features that are not incorporated into the standard interkernel pipes.
To separate this host pipe implementation from the existing interkernel pipe implementation, host pipes are declared in a different namespace than interkernel pipes.
This namespace is as follows:
Host pipe support is enabled by including the following file:
Additionally, this prototype implementation of host pipes relies on USM for simulation. When simulating your IP for verification in a SYCL* program, you can use only boards and devices that support USM with host pipes.
- Declare a Host Pipe
- Host Pipe API
- Host Pipes IP Authoring Flow
- Host Pipes RTL Interfaces
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