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Synthesizing Your Component IP with Intel® Quartus® Prime Software
When you are satisfied with the predicted performance of your component, use Intel® Quartus® Prime software to synthesize your component. Synthesis also generates accurate area and performance (fMAX) estimates for your design. However, your design is not expected to cleanly close timing in the Intel® Quartus® Prime reports.
You can expect to see timing closure warnings in the Intel® Quartus® Prime logs because the generated project targets a clock speed of 1000 MHz to achieve the best possible placement for your design. The fMAX value presented in the FPGA optimization report estimates the maximum clock rate your component can cleanly close timing for.
After the Intel® Quartus® Prime compilation is completed, the summary section of the FPGA optimization report shows the area and performance data for your components. These estimates are more accurate than estimates generated when you compile your IP component for simulation only.
Typically, Intel® Quartus® Prime compilation times can take minutes to hours, depending on the size and complexity of your IP components.
To synthesize your component IP and generate quality of results (QoR) data, instruct the compiler to run the Intel® Quartus® Prime compilation flow automatically after synthesizing the components. Include the –Xshardware option in your icpx -fsycl command:
icpx -fsycl -fintelfpga -Xshardware -Xstarget="<FPGA device family or part number>"...
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