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Why is FPGA Compilation Different?
Types of SYCL* FPGA Compilation
FPGA Compilation Flags
Emulate and Debug Your Design
Evaluate Your Kernel Through Simulation
Device Selectors for FPGA
FPGA IP Authoring Flow
Fast Recompile for FPGA
Generate Multiple FPGA Images (Linux only)
FPGA BSPs and Boards
Targeting Multiple Homogeneous FPGA Devices
Targeting Multiple Platforms
FPGA-CPU Interaction
FPGA Performance Optimization
Use of RTL Libraries for FPGA
Use SYCL Shared Library With Third-Party Applications
FPGA Workflows in IDEs
Intel oneAPI DPC++ Library (oneDPL)
Intel oneAPI Math Kernel Library (oneMKL)
Intel oneAPI Threading Building Blocks (oneTBB)
Intel oneAPI Data Analytics Library (oneDAL)
Intel oneAPI Collective Communications Library (oneCCL)
Intel oneAPI Deep Neural Network Library (oneDNN)
Intel oneAPI Video Processing Library (oneVPL)
Other Libraries
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Host Pipes RTL Interfaces
This section provides a summary of interfacing with host pipes in your IP based on the choice of protocol.
Host pipes support Avalon streaming and memory-mapped interfaces. Refer to the Intel® Avalon Interface Specifications for details about these protocols.
For AVALON_MM protocols, register addresses in the CRA are specified in the generated kernel header file in the project directory. Refer to Example Register Map File for further details on CRA agent registers.
AVALON_STREAMING_USES_READY Protocol
This protocol allows the sink to backpressure by deasserting the ready signal asserted. The sink signifies that it is ready to consume data by asserting the ready signal. On the cycle where the sink asserts the ready signal, the source must wait for the ready_latency signal to cycle before responding with valid and data signals, where the template parameter specifies the ready_latency in the host pipe dec
Host-to-Device Pipe
When the uses_valid template parameter is set to false and the ready signal is asserted by the kernel and sampled by the host, the host must wait ready_latency cycles before the value on the data interface is sampled by the kernel and consumed.
When the uses_valid template parameter is set to true and the ready signal is asserted by the kernel and sampled by the host, the host must wait ready_latency cycles before valid, and the data interface is sampled by the kernel and consumed.
Device-to-Host Pipe
When the uses_valid template parameter is set to true and the host asserts the ready signal, the kernel replies with valid=1 and qualified data (if available) ready_latency cycles after the corresponding ready was first asserted.
When the uses_valid template parameter is set to false and the host asserts the ready signal, the kernel replies with qualified data ready_latency cycles after the corresponding ready was first asserted.
AVALON_STREAMING_ALWAYS_READY Protocol
With this choice of protocol, no ready signal is exposed by the host pipe, and the sink cannot backpressure.
The valid signal qualifies data transfer from source to sink per cycle when the uses_valid template parameter is set to true. When the uses_valid template parameter is set to false, the source implicitly provides a valid output on every cycle, and the sink assumes a valid input on every cycle.
Host-to-Device Pipe
When the uses_valid template parameter is set to false, the kernel samples and processes the value on the host pipe data interfaces on each cycle.
When the uses_valid template parameter is set to true, the kernel samples and processes the value on the host pipe data interface on each cycle that the valid signal is asserted.
Device-to-Host Pipe
When the uses_valid template parameter is set to false, the host must sample and process values on the host pipe data interface every clock cycle. Failure to do so causes the data to be dropped.
When the uses_valid template parameter is set to true, the host must sample and process values on the host pipe data interface every clock cycle that the valid signal is asserted. Failure to do so causes the data to be dropped.
AVALON_MM Protocol
With this protocol, an implicit ready signal is held high, and the sink cannot backpressure.
Intel does not recommend using this protocol with device-to-host pipes. The uses_valid template parameter must also be set to true. Both the valid and data signals for the pipe are stored in registers implemented in the CRA agent.
Host-to-Device Pipe
The host writes a 1 to the valid register to indicate that the value in the data register is qualified. When the kernel has consumed this data, the kernel automatically clears the value in the valid register. A cleared valid register signifies that the host is free to write a new value into the data register.
AVALON_MM_USES_READY Protocol
With this protocol, an additional register in the CRA is created to hold the ready signal. You must set the uses_valid template parameter to true.
Host-to-Device Pipe
The kernel writes a 1 to the ready register when it is available to receive data. The host writes a 1 to the valid register to indicate that the value in the data register is qualified.
Device-to-Host Pipe
The kernel writes a 1 to the valid register to indicate that the value in the data register is qualified. This value is held in the data register until the host writes a 1 to the ready register, which signifies that the host has consumed valid data from the data register. The kernel clears the ready register when the kernel has written subsequent qualified data and the valid register.
Avalon Packet Sideband Signals
Avalon packet sideband signal support is enabled by including the host_pipes.hpp header and defining host pipes using the AvalonPacketstruct defined in the following header file:
$INTELFPGAOCLSDKROOT/include/sycl/ext/intel/prototype/pipes_ext.hpp
Using the AvalonPacket struct with the uses_packets template parameter set to true adds two additional 1-bit signals to the Avalon interface, start_of_packet (sop), and end_of_packet (eop).
Assert the sop signal when you send the first packet along with a valid signal assertion. Assert the eop signal when you send the last packet, along with a valid signal assertion. You can assert sop and eop signals in the same cycle for a single packet transfer transaction. The sop signal can also be asserted on the cycle immediately after the eop signal was asserted for the previous packet.
The third template parameter for the AvalonPacketstruct signifies uses_empty. When uses_empty is set to true, it adds an extra empty signal that is 
bits long. The empty signal indicates the number of symbols that are empty during the eop cycle.
Empty symbols are always the last symbols in the data. That is, the symbols carried by low-order bits when first_symbol_In_high_order_bits is true, or the high-order bits if first_symbol_In_high_order_bits is set to false.
Setting uses_empty is required for all packet interfaces carrying more than one symbol of data that have a variable length packet format.
Avalon Packet Sideband Signals Example
The following example uses the AvalonPacket struct with the uses_packets and users_empty template parameters both set to true. The size of the PipeData type should be a multiple of the number of bits per symbol.
using PipeData = ac_int<kBitsPerSymbol * kSymbolsPerBeat, false>; using Packet = sycl::ext::intel::experimental::AvalonPacket<PipeData, true, true>;
When you define the host pipe, set the data type to the AvalonPacket struct:
using H2DPipe = sycl::ext::intel::prototype::pipe<H2DPipeID, Packet, kPipeMinCapacity, kReadyLatency, kBitsPerSymbol, true, true, protocol_name::AVALON_STREAMING_USES_READY>;
The following code example instantiates a packet struct and writes to the pipe (from the host):
bool sop = true; bool eop = false; int empty = 0; PipeData data = ... Packet in_packet(data, sop, eop, empty); H2DPipe::write(q, in_packet);
The following code example reads from the pipe and extracts the packet signals (from device):
Packet in_packet = H2DPipe::read(); PipeData in_data = in_packet.data; bool sop = in_packet.sop; bool eop = in_packet.eop; int empty = in_packet.empty;
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