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Emulate and Debug Your IP Component
Verify the functionality of your design by compiling your component and testbench to an x86-64 FPGA emulation executable that you can debug with a oneAPI debugger. This process is sometimes referred to as debugging through emulation.
Compiling your design to an x86-64 executable is faster than generating and simulating RTL. Shorter compilation time allows you to debug and refine your component quickly before verifying how your component is implemented in hardware.
No additional software is required to emulate your IP component, and no modifications to your host code are required.
You can compile your component and testbench to an x86-64 executable for functional verification using the icpx -fscyl -fintelfpga <source>.cpp command.
To verify the design functionality from the x86-64 emulation of your testbench and component, use one of the following debugging techniques:
Running the program to see if it generates the expected output.
Using print statements in your code (such as printf or std::cout) to output variable values at specific points.
Stepping through your code with a debugger.
If you want to step through your code with a debugger, ensure that you set the compiler command to include debug information and to generate unoptimized binary files. Debug versions of your executables are generated by default, so a command option such as -ggdb is unnecessary.
To disable debug information, add the -g0 option to your icpx compiler command.
On Linux systems, you can use the GDB provided with the Intel® oneAPI Base Toolkit to debug your component and testbench.
You can automate the process by using a Makefile or batch script. Use the Makefiles and scripts provided in the Intel® oneAPI Base Toolkit example designs and tutorials as guides for creating your Makefiles or batch scripts.
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