As mentioned earlier in Types of FPGA Compilation, generating an FPGA hardware image requires Intel® Quartus® Prime software, to map your design from RTL to the FPGA’s primitive hardware resources. For BSPs necessary to compile to FPGA hardware, refer to the Intel® FPGA development flow webpage.
What is a Board?
Like a GPU, an FPGA is an integrated circuit that must be mounted onto a card or a board to interface with a server or a desktop computer. In addition to the FPGA, the board provides memory, power, and thermal management, and physical interfaces to allow the FPGA to communicate with other devices.
What is a BSP?
A BSP consists of software layers and an FPGA hardware scaffold design that makes it possible to target the FPGA through the Intel® oneAPI DPC++/C++ Compiler. The FPGA design generated by the compiler is stitched into the framework provided by the BSP.
What is Board Variant?
A BSP can provide multiple board variants that support different functionality. For example, the intel_s10sx_pac BSP contains two variants that differ in their support for Unified Shared Memory (USM). For additional information about USM, refer to the Unified Shared Memory and USM Interfaces topics in the SYCL Reference Documentation.
A board can be supported by more than one BSP and a BSP might support more than one board variant.
The Intel® FPGA Add-On for oneAPI Base Toolkit provides BSPs for two boards and board variants provided by these BSPs can be selected using the following flags in your icpx -fsycl command:
- The (part of the Intel® oneAPI Base Toolkit) provides partial BSPs sufficient for generating the FPGA early image and optimization report. In contrast, the Intel® FPGA Add-On for oneAPI Base Toolkit provides full BSPs, which are necessary for generating the FPGA hardware image.
When running an executable on an FPGA board, you must ensure that you have initialized the FPGA board for the board variant that the executable is targeting. For information about initializing an FPGA board, refer to FPGA Board Initialization.
For information about FPGA optimizations possible with Restricted USM, refer to Prepinning and Zero-Copy Memory Access topics in the FPGA Optimization Guide for Intel® oneAPI Toolkits.