FPGA Optimization Guide for Intel® oneAPI Toolkits

Developer Guide

Contents

Zero-Copy Memory Access

Prior to the implementation of restricted USM, you had to access host’s data from the device using one of the following methods:
  • Through SYCL buffers
  • By copying data between the host and the device using explicit USM
Both of these methods resulted in data transfers between the host and the device memory on discrete cards such as the Intel® FPGA Programmable Acceleration Card (PAC) D5005 (previously known as
Intel® FPGA Programmable Acceleration Card (PAC) with Intel® Stratix® 10 SX FPGA
).
With host allocations on devices supporting restricted USM, a kernel can directly access data over PCIe (no copying required). By using host allocations in designs that have infrequent random accesses to large pieces of data, you can improve throughput and latency of the design as a large piece of data no longer requires copying in full to the device. For detailed explanation of this concept, refer to the Zero-copy Data Transfer tutorial on GitHub.
  • SYCL buffers created with host allocations set as
    hostData
     in the constructor still result in data copy from the host to the device memory. For more information, refer to Prepinning Memory.
  • Shared allocation for the
    pac_s10_usm
     board     that is in the
    intel_s10sx_pac
     BSP     does not yield any change in the behavior or performance over host allocation. Both its host and shared allocations reside in the host.
For additional information, refer to the FPGA tutorial sample
Zero-copy Data Transfer
 listed in the Intel® oneAPI Samples Browser on Linux* or Windows*, or access the code sample in GitHub.
Unified Shared Memory (USM) Interfaces

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.