Visible to Intel only — GUID: GUID-8B4B96FB-55E0-41F1-8C60-763F12CEE89F
Refactor the Loop-Carried Data Dependency
Relax Loop-Carried Dependency
Transfer Loop-Carried Dependency to Local Memory
Minimize the Memory Dependencies for Loop Pipelining
Unroll Loops
Fuse Loops to Reduce Overhead and Improve Performance
Optimize Loops With Loop Speculation
Remove Loop Bottlenecks
Shannonization to Improve FMAX/II
Optimize Inner Loop Throughput
Improve Loop Performance by Caching On-Chip Memory
Global Memory Bandwidth Use Calculation
Manual Partition of Global Memory
Partitioning Buffers Across Different Memory Types (Heterogeneous Memory)
Partitioning Buffers Across Memory Channels of the Same Memory Type
Ignoring Dependencies Between Accessor Arguments
Contiguous Memory Accesses
Static Memory Coalescing
Conversion Rules for <span class='codeph'>ap_float</span>
Operations with Explicit Precision Controls
Comparison Operators
Additional <span class='codeph'>ap_float</span> Functions
Additional Data Types Provided by the <span class='codeph'>ap_float.hpp</span> Header File
Quality of Results and the ap_float Data Type
Specify Schedule FMAX Target for Kernels (<span class='codeph'>-Xsclock=<clock target>)
Disable Burst-Interleaving of Global Memory (<span class='codeph'>-Xsno-interleaving=<global_memory_type></span>)
Force Ring Interconnect for Global Memory (<span class='codeph'>-Xsglobal-ring</span>)
Force a Single Store Ring to Reduce Area (<span class='codeph'>-Xsforce-single-store-ring</span>)
Force Fewer Read Data Reorder Units to Reduce Area (<span class='codeph'>-Xsnum-reorder</span>)
Disable Hardware Kernel Invocation Queue (<span class='codeph'>-Xsno-hardware-kernel-invocation-queue</span>)
Modify the Handshaking Protocol Between Clusters (<span class='codeph'>-Xshyper-optimized-handshaking</span>)
Disable Automatic Fusion of Loops (<span class='codeph'>-Xsdisable-auto-loop-fusion</span>)
Fuse Adjacent Loops With Unequal Trip Counts (<span class='codeph'>-Xsenable-unequal-tc-fusion</span>)
Pipeline Loops in Non-task Kernels (<span class='codeph'>-Xsauto-pipeline</span>)
Control Semantics of Floating-Point Operations (<span class='codeph'>-fp-model=<var><value></var> </span>)
Modify the Rounding Mode of Floating-point Operations (<span class='codeph'>-Xsrounding=<rounding_type></span>)
Global Control of Exit FIFO Latency of Stall-free Clusters (<span class='codeph'>-Xssfc-exit-fifo-type=<var><value></var> </span>)
Enable the Read-Only Cache for Read-Only Accessors (<span class='codeph'>-Xsread-only-cache-size=<var><N></var>)</span>
Control Hardware Implementation of the Supported Data Types and Math Operations (<span class='codeph'>-Xsdsp-mode=<var><option></var> </span>)
Specify Schedule FMAX Target for Kernels
Specify a Workgroup Size
Specify Number of SIMD WorkItems
Omit Hardware that Generates and Dispatches Kernel IDs
Omit Hardware to Support the <span class='codeph'>no_global_work_offset</span> Attribute in <span class='codeph'>parallel_for</span> Kernels
Reduce Kernel Area and Latency
<span class='codeph'>disable_loop_pipelining</span> Attribute
<span class='codeph'>initiation_interval</span> Attribute
<span class='codeph'>ivdep</span> Attribute
<span class='codeph'>loop_coalesce</span> Attribute
<span class='codeph'>max_concurrency</span> Attribute
<span class='codeph'>max_interleaving</span> Attribute
<span class='codeph'>speculated_iterations</span> Attribute
<span class='codeph'>unroll</span> Pragma
Loop Fuse Functions and <span class='codeph'>nofusion</span> Attribute
Algorithmic C Data Types
Floating Point Pragmas
FPGA Accessor Properties
FPGA Extensions
FPGA Kernel Attributes
FPGA Local Memory Function
Latency Control Properties (Beta)
FPGA LSU Controls
FPGA Loop Directives
FPGA Memory Attributes
FPGA Optimization Flags
Pipe API
<span class='codeph'>task_sequence</span> Template Parameters and Function APIs
Visible to Intel only — GUID: GUID-8B4B96FB-55E0-41F1-8C60-763F12CEE89F
Data Types and Operations
Data Type Selection Considerations
Select the appropriate data type to optimize the FPGA area use by your SYCL* application:
- Select the most appropriate data type for your application. For example, do not define your variable as float if the data type short is sufficient.
- Ensure that both sides of an arithmetic expression belong to the same data type. Consider an example where one side of an arithmetic expression is a floating-point value and the other side is an integer. The mismatched data types cause the Intel® oneAPI DPC++/C++ Compiler to create implicit conversion operators, which can become expensive if they are present in large numbers.
- Take advantage of padding if it exists in your data structures. For example, if you only need float3 data type, which has the same size as float4, you may change the data type to float4 to make use of the extra dimension to carry an unrelated value.
Arithmetic Operation Considerations
Select the appropriate arithmetic operation for your SYCL application to avoid excessive FPGA area use.
- Introduce floating-point arithmetic operations only when necessary.
- The Intel® oneAPI DPC++/C++ Compiler defaults floating-point constants to double data type. Add an f designation to the constant to make it a single precision floating-point operation. For example, the arithmetic operation sin(1.0) represents a double precision floating-point sine function. The arithmetic operation sin(1.0f) represents a single precision floating-point sine function.
- If you do not require full precision result for a complex function, compute simpler arithmetic operations to approximate the result. Consider the following example scenarios:
- Instead of computing the function pow(x,n) where n is a small value, approximate the result by performing repeated squaring operations because they require much less hardware resources and area.
- Ensure you are aware of the original and approximated area uses because in some cases, computing a result via approximation might result in excess area use. For example, the sqrt function is not resource-intensive. Other than a rough approximation, replacing the sqrt function with arithmetic operations that the host must compute at runtime might result in larger area use.
- If your kernel performs a complex arithmetic operation with a constant that the Intel® oneAPI DPC++/C++ Compiler computes at compilation time (for example, log(PI/2.0)), perform the arithmetic operation on the host instead and pass the result as an argument to the kernel at runtime.
RESTRICTION:
Currently, SYCL implementation of math functions is not supported on FPGAs.
Parent topic: Resource Use