Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

ID 767853
Date 12/16/2022

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Document Table of Contents

Restrictions of Pipes

The following table summarizes restrictions of pipes:

Restrictions of Pipes



Multiple Pipe Call Sites

A kernel can read from the same pipe multiple times. However, multiple kernels cannot read from the same pipe. Similarly, a kernel can write to the same pipe multiple times, but multiple kernels cannot write to the same pipe.

Feedback and Feed-Forward Pipes

Within a single kernel, you should either read from a pipe or write to a pipe. Writing and reading to the same pipe within a single kernel may lead to poor performance.

Emulation Support

The FPGA emulator supports emulation of kernels that contain pipes. For better conformity between emulation and hardware, provide a non-zero pipe capacity while specializing a pipe type. For more information about the Emulator, refer to the Intel® oneAPI Programming Guide.


If the same kernel is invoked more than once, the FPGA emulator may attempt to execute kernels concurrently, resulting in a data race if both invocations attempt to read or write from the same pipe. This issue affects only emulation. In the hardware flow, multiple invocations of the same kernel are executed serially. To work around this issue, add a call to the sycl::queue::wait() function between executions of the same kernel.

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