Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

ID 767853
Date 12/16/2022
Public

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Document Table of Contents

FPGA LSU Controls

The following table summarizes the load-store unit (LSU) control:
LSU Controls
Syntax Description Example
ext::intel::lsu<…>;

Allows you to specify LSU attributes to control the LSU inferred by the compiler.

No attributes attempt to infer a pipelined LSU.

For example:

  • ext::intel::burst_coalesce<true>
  • ext::intel::statically_coalesce<false>
  • ext::intel::prefetch<true>
  • ext::intel::cache<1024>

#include <sycl/ext/intel/fpga_extensions.hpp>

using namespace sycl
…
using BurstCoalescedLSU = ext::intel::lsu<ext::intel::burst_coalesce<true>,
                                          ext::intel::statically_coalesce<false>>;
                                 
BurstCoalescedLSU::store(output_ptr, X);