Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

ID 767853
Date 12/16/2022
Public

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Instrument the Kernel Pipeline with Performance Counters (<span class='codeph'>-Xsprofile</span>)

Enable profiling during design compilation to add profiling counters to the SYCL kernel pipeline. To instrument the SYCL code with performance counters, add the -Xsprofile flag to your compiler command.

NOTE:
  • Instrumenting the design with performance counters increases hardware resource utilization (that is, increases FPGA area use) and typically decreases performance.
  • Ensure that all kernel names are unique so that the dynamic profiler interprets the results correctly.
CAUTION:

In large designs, the overhead from profiling can cause fMAX degradation. It may also prevent the design from fitting on the chip due to the area overhead of the profiling counters.