Programming Guide


FPGA BSPs and Boards

As mentioned earlier in Types of DPC++ FPGA Compilation, generating an FPGA hardware image requires the Intel® FPGA Add-On for oneAPI Base Toolkit, which provides the Intel® Quartus® Prime Software that maps your design from RTL to the FPGA’s primitive hardware resources. Additionally, this add-on package provides basic Board Support Packages (BSPs) that can be used to compile to FPGA hardware.

What is a Board?

Similar to a GPU, an FPGA is an integrated circuit that must be mounted onto a card or a board to interface with a server or a desktop computer. In addition to the FPGA, the board provides memory, power, and thermal management, and physical interfaces to allow the FPGA to communicate with other devices.

What is a BSP?

A BSP consists of software layers and an FPGA hardware scaffold design that makes it possible to target the FPGA through the
Intel® oneAPI
. The FPGA design generated by the compiler is stitched into the framework provided by the BSP.

What is Board Variant?

A BSP can provide multiple board variants, that support different functionality. For example, the
BSP contains two variants that differ in their support for Unified Shared Memory (USM). For additional information about USM, refer to the Unified Shared Memory topic in the
Intel® oneAPI
Developer Guide and Reference
A board can be supported by more than one BSP and a BSP might support more than one board variant.
The Intel® FPGA Add-On for oneAPI Base Toolkit provides BSPs for two boards and board variants provided by these BSPs can be selected using the following flags in your
USM Support
Explicit USM
(previously known as
Intel® PAC with Intel® Stratix® 10 SX FPGA
Explicit USM
Explicit USM
Restricted USM
  • The
    Intel® oneAPI
    (part of the Intel® oneAPI Base Toolkit) provides partial BSPs sufficient for generating the FPGA early image and optimization report. In contrast, the Intel® FPGA Add-On for oneAPI Base Toolkit provides full BSPs, which are necessary for generating the FPGA hardware image.
  • When running a DPC++ executable on an FPGA board, you must ensure that you have initialized the FPGA board for the board variant that the executable is targeting. For information about initializing an FPGA board, refer to FPGA Board Initialization.
  • For information about FPGA optimizations possible with Restricted USM, refer to Prepinning and Zero-Copy Memory Access topics in the Intel® oneAPI DPC++ FPGA Optimization Guide.

Custom BSPs

In addition to the BSPs described above, you can also use custom BSPs provided by a board vendor. Follow these steps to use the
Intel® oneAPI
with a custom BSP:
  1. Install the Intel® FPGA Add-On for Intel® Custom Platform package that contains the version of Intel® Quartus® Prime Software required by the custom BSP. Refer to the detailed instructions in the Intel oneAPI Toolkits Installation Guide.
  2. Place the full custom BSP in the
    directory of the add-on installation.
  3. Follow all installation instructions provided by the BSP vendor.

Product and Performance Information


Performance varies by use, configuration and other factors. Learn more at