A newer version of this document is available. Customers should click here to go to the newest version.
Why is FPGA Compilation Different? Types of SYCL* FPGA Compilation FPGA Compilation Flags Emulate and Debug Your Design Evaluate Your Kernel Through Simulation Device Selectors for FPGA FPGA IP Authoring Flow Fast Recompile for FPGA Generate Multiple FPGA Images (Linux only) FPGA BSPs and Boards Targeting Multiple Homogeneous FPGA Devices Targeting Multiple Platforms FPGA-CPU Interaction FPGA Performance Optimization Use of RTL Libraries for FPGA Use SYCL Shared Library With Third-Party Applications FPGA Workflows in IDEs
Intel oneAPI DPC++ Library (oneDPL) Intel oneAPI Math Kernel Library (oneMKL) Intel oneAPI Threading Building Blocks (oneTBB) Intel oneAPI Data Analytics Library (oneDAL) Intel oneAPI Collective Communications Library (oneCCL) Intel oneAPI Deep Neural Network Library (oneDNN) Intel oneAPI Video Processing Library (oneVPL) Other Libraries
Code IP Components in SYCL*
When you write IP components in SYCL, consider these additional requirements and techniques.
- Customize RTL Interfaces
- Suggested Coding Styles
- Memory-Mapped interfaces
- Host Pipes
- Agent IP Component Kernels
- Streaming IP Component Kernels
- Streaming Arguments
- Pipelined Kernels
- Stable Arguments
- The printf Command
Did you find the information on this page useful?