Visible to Intel only — GUID: GUID-04F283B6-4F97-4C8B-B10C-66551444949B
Why is FPGA Compilation Different?
Types of SYCL* FPGA Compilation
FPGA Compilation Flags
Emulate and Debug Your Design
Evaluate Your Kernel Through Simulation
Device Selectors for FPGA
FPGA IP Authoring Flow
Fast Recompile for FPGA
Generate Multiple FPGA Images (Linux only)
FPGA BSPs and Boards
Targeting Multiple Homogeneous FPGA Devices
Targeting Multiple Platforms
FPGA-CPU Interaction
FPGA Performance Optimization
Use of RTL Libraries for FPGA
Use SYCL Shared Library With Third-Party Applications
FPGA Workflows in IDEs
Intel oneAPI DPC++ Library (oneDPL)
Intel oneAPI Math Kernel Library (oneMKL)
Intel oneAPI Threading Building Blocks (oneTBB)
Intel oneAPI Data Analytics Library (oneDAL)
Intel oneAPI Collective Communications Library (oneCCL)
Intel oneAPI Deep Neural Network Library (oneDNN)
Intel oneAPI Video Processing Library (oneVPL)
Other Libraries
Visible to Intel only — GUID: GUID-04F283B6-4F97-4C8B-B10C-66551444949B
Restrictions and Limitations in RTL Support
When creating your RTL module for use inside SYCL kernels, ensure that the RTL module operates within the following restrictions:
An RTL module must use a single input Avalon® streaming interface. A single pair of ready and valid logic must control all the inputs. You have the option to provide the necessary Avalon® streaming interface ports but declare the RTL module as stall-free. In this case, you do not have to implement proper stall behavior because the Intel® oneAPI DPC++/C++ Compiler creates a wrapper for your module. Refer to Object Manifest File Syntax of an RTL Module for additional information.
NOTE:You must handle ivalid signals properly if your RTL module has an internal state. Refer to Stall-Free RTL for more information.The RTL module must work correctly regardless of the kernel clock frequency.
RTL modules cannot connect to external I/O signals. All input and output signals must come from a SYCL kernel.
An RTL module must have a clock port, a resetn port, and Avalon® streaming interface input and output ports (that is, ivalid, ovalid, iready, oready). Name the ports as specified here.
RTL modules that communicate with external memory must have Avalon® memory-mapped interface port parameters that match the corresponding Custom Platform parameters. The Intel® oneAPI DPC++/C++ Compiler does not perform any width or burst adaptation.
RTL modules that communicate with external memory must behave as follows:
They cannot burst across the burst boundary.
They cannot make requests every clock cycle and stall the hardware by monopolizing the arbitration logic. An RTL module must pause its requests regularly to allow other load or store units to execute their operations.
RTL modules cannot act as stand-alone SYCL kernels. RTL modules can only be helper functions and be integrated into a SYCL kernel during kernel compilation.
Every function call corresponding to RTL module instantiation is independent of other instantiations. There is no hardware sharing.
Do not incorporate kernel code into a SYCL library file. Incorporating kernel code into the library file causes the offline compiler to issue an error message. You may incorporate helper functions into the library file.
An RTL component must receive all its inputs at the same time. A single ivalid input signifies that all inputs contain valid data.
You can only set RTL module parameters in the <RTL module description file name>.xml specification file and not in the SYCL kernel source file. To use the same RTL module with multiple parameters, create a separate FUNCTION tag for each parameter combination.
You can only pass data inputs to an RTL module by value via the SYCL kernel code. Do not pass data inputs to an RTL module via pass-by-reference, structs, or channels. In the case of channel data, pass the extracted scalar data.
NOTE:Passing data inputs to an RTL module via pass-by-reference or structs causes a fatal error in the offline compiler.The debugger (for example, GDB for Linux) cannot step into a library function during emulation if the library is built without the debug information. However, irrespective of whether the library is built with or without the debug data, optimization and area reports are not mapped to the individual code line numbers inside a library.
Names of RTL module source files cannot conflict with the file names of Intel® oneAPI DPC++/C++ Compiler IP. Both the RTL module source files and the compiler IP files are stored in the <kernel file name>/system/synthesis/submodules directory. Naming conflicts cause existing compiler IP files in the directory to be overwritten by the RTL module source files.
The compiler does not support .qip files. You must manually parse nested .qip files to create a flat list of RTL files.
TIP:It is challenging to debug an RTL module that works correctly on its own but works incorrectly as part of a SYCL kernel. Double-check all parameters under the ATTRIBUTES element in the <RTL object manifest file name>.xml file.All compiler area estimation tools assume that the RTL module area is 0. The compiler does not currently support specifying an area model for RTL modules.