Intel® FPGA SDK for OpenCL™ Pro Edition: Programming Guide

ID 683846
Date 12/13/2021
Public

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11.1.2.3. Stall-Free RTL

The Intel® FPGA SDK for OpenCL™ Offline Compiler can optimize hardware resource usage and performance by removing stall logic around an RTL module with fixed latency.
An RTL module that has a variable latency and uses Avalon® streaming interface input and output signals can wait until input data is ready. Conversely, the Intel® FPGA SDK for OpenCL™ pipeline can stall until it receives valid output data from the RTL module. For an RTL module with a fixed latency, you can remove an RTL stall by modifying the object manifest file (.xml), as described below.
  1. To instruct the offline compiler to remove stall logic around the RTL module, if appropriate, set the IS_STALL_FREE attribute under the FUNCTION element to "yes".
    This modification informs the offline compiler that the RTL module produces valid data every EXPECTED_LATENCY cycle(s).
    Note: EXPECTED_LATENCY is an attribute you specify in the .xml file under the FUNCTION element.
  2. Specify a value for EXPECTED_LATENCY such that the latency equals the number of pipeline stages in the module.
    CAUTION:
    An inaccurate EXPECTED_LATENCY value causes the RTL module to be out of sync with the rest of the pipeline.

A stall-free RTL module might receive an invalid input signal (that is, ivalid is low). In this case, the module ignores the input and produces invalid data on the output. For a stall-free RTL module without an internal state, it might be easier to propagate the invalid input through the module. However, for an RTL module with an internal state, you must handle an ivalid=0 input carefully.

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