ID 683846
Date 12/13/2021
Public

## 11.1.2.7.2. XML Elements for INTERFACE

In the object manifest file of the RTL module within an Intel® FPGA SDK for OpenCL™ library, there are XML elements under INTERFACE that you can define to specify aspects of the RTL module's interface (for example, Avalon® streaming interface).
Table 15.  Mandatory XML Elements Associated with the INTERFACE Element in the Object Manifest File of an RTL Module
XML Element Description
INPUT

Specifies the input parameter of the RTL module.

INPUT attributes:

• port—Specifies the port name of the RTL module.
• width—Specifies the width of the port in bits.

The input parameters are concatenated to form the input stream.

Aggregate data structures such as structs and arrays are not supported as input parameters.

OUTPUT

Specifies the output parameter of the RTL module.

OUTPUT attributes:

• port—Specifies the port name of the RTL module.
• width—Specifies the width of the port in bits.

The return value from the input stream is sent out via the output parameter on the output stream.

Aggregate data structures such as structs and arrays are not supported as input parameters.

Table 16.  Additional XML Elements to Support External Memory Access
XML Element Description
MEM_INPUT

Describes a pointer input to the RTL module.

MEM_INPUT attributes:

• port—Specifies the name of the pointer input.
• access—Specifies to the Intel® FPGA SDK for OpenCL™ Offline Compiler how the RTL module uses this pointer. Valid access values are readonly and readwrite. If the RTL module only writes with this pointer, assign readwrite to access.

Because all pointers to external memory must be 64 bits, there is no width attribute associated with MEM_INPUT.

AVALON_MEM

Declares the Avalon® memory-mapped interface for your RTL module.

AVALON_MEM attributes:

• port—Specifies the root of the corresponding port names in the RTL module. For example, if port has a value of avm_port0_, the names of all Avalon® memory-mapped interface ports for the RTL module starts with avm_port0_.
• width—Specifies the data width, which must match the corresponding width value in the accelerator board's board_spec.xml file. Within the board_spec.xml file, the width value is specified in the interface element under global_mem.

For more information, refer to the global_mem section under XML Elements, Attributes, and Parameters in the board_spec.xml File in the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide.

• burstwidth—Specifies the number of bits required to represent burst size. Use burstwidth = log(maxburst) +1 to calculate the burst size, where maxburst is the corresponding maximum burst size specified in the board_spec.xml file. For example, if maxburst=16, burstwidth=5.
• optype—Specifies either the Avalon® memory-mapped port is reading (read) or writing (write) from external memory. You can only assign either read or write to optype.

For the AVALON_MEM element defined in the code example above, the corresponding RTL module ports are as follows:

output         avm_port0_enable,
input          avm_port0_waitrequest,
output [4:0]   avm_port0_burstcount,