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Evaluate Your IP Component Through Simulation
When you compile your component to an Intel® FPGA device family or part number with the -Xstarget compiler option, the Intel oneAPI DPC++/C++ Compiler links your design C++ testbench with an RTL-compiled version of your component that runs in an RTL simulator.
Use Siemens® EDA Questa® software to perform the simulation. You must have Questa® simulation software installed when authoring IP components with the Intel oneAPI Base Toolkit. For a list of supported versions of the Questa® software, refer to the EDA Interface Information section in the Intel® Quartus® Prime Software and Device Support Release Notes.
Verifying the functionality of your design in this way is sometimes called debugging through simulation.
To verify the design functionality from your design simulation, use the following debugging techniques:
Run the executable that the compiler generates by targeting the FPGA device. By default, the executable name is a.out (Linux). For example, you might invoke a command like one of the following commands for a simple single-file design:
icpx -fsycl -fintelfpga -Xssimulation -Xstarget="Arria10" […] design.cpp
env CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1 ./a.out
Write variable values to output pipes or mm_host interfaces at certain points in your code.
Review the waveforms generated when running your design.
The compiler does not log signals by default when you compile your design. To enable signal logging in simulation, refer to Debug During Verification.
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