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Why is FPGA Compilation Different? Types of SYCL* FPGA Compilation FPGA Compilation Flags Emulate and Debug Your Design Evaluate Your Kernel Through Simulation Device Selectors for FPGA FPGA IP Authoring Flow Fast Recompile for FPGA Generate Multiple FPGA Images (Linux only) FPGA BSPs and Boards Targeting Multiple Homogeneous FPGA Devices Targeting Multiple Platforms FPGA-CPU Interaction FPGA Performance Optimization Use of RTL Libraries for FPGA Use SYCL Shared Library With Third-Party Applications FPGA Workflows in IDEs
Intel oneAPI DPC++ Library (oneDPL) Intel oneAPI Math Kernel Library (oneMKL) Intel oneAPI Threading Building Blocks (oneTBB) Intel oneAPI Data Analytics Library (oneDAL) Intel oneAPI Collective Communications Library (oneCCL) Intel oneAPI Deep Neural Network Library (oneDNN) Intel oneAPI Video Processing Library (oneVPL) Other Libraries
Ahead-of-Time Compilation for CPU Architectures
In ahead-of-time (AOT) compilation mode, optimization flags can be used to produce code aimed to run better on a specific CPU architecture.
icpx -fsycl -fsycl-targets=spir64_x86_64 -Xs “-device <CPU optimization flags>” a.cpp b.cpp -o app.out
Supported CPU optimization flags are:
-march=<instruction_set_arch> Set target instruction set architecture: 'sse42' for Intel® Streaming SIMD Extensions 4.2 'avx2' for Intel® Advanced Vector Extensions 2 'avx512' for Intel® Advanced Vector Extensions 512
NOTE:The set of supported optimization flags may be changed in future releases.
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